JPWO2015068251A1 - 半導体装置およびその製造方法 - Google Patents
半導体装置およびその製造方法 Download PDFInfo
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- JPWO2015068251A1 JPWO2015068251A1 JP2014540661A JP2014540661A JPWO2015068251A1 JP WO2015068251 A1 JPWO2015068251 A1 JP WO2015068251A1 JP 2014540661 A JP2014540661 A JP 2014540661A JP 2014540661 A JP2014540661 A JP 2014540661A JP WO2015068251 A1 JPWO2015068251 A1 JP WO2015068251A1
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- insulating film
- film
- interlayer insulating
- wiring
- semiconductor device
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Classifications
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- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
- H01L23/528—Geometry or layout of the interconnection structure
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Abstract
Description
図1は、本実施の形態の半導体装置の断面構造を示す要部断面図である。
本実施の形態2は、上記実施の形態1の変形例であり、実施の形態1とは、第1電界緩和層ER1および第2電界緩和層ER2の形成方法とアンモニアプラズマ処理の条件が異なり、その他の部分は同様である。本実施の形態2では、第1電界緩和層ER1は第2層間絶縁膜INS2の形成工程中に、第2電界緩和層ER2は第3層間絶縁膜INS3の形成中に形成される。従って、アンモニアプラズマ処理工程で第1ダメージ層DM1および第2ダメージ層DM2が形成されるが、第1電界緩和層ER1および第2電界緩和層ER2は形成されない。図15は、第2層間絶縁膜INS2および第3層間絶縁膜INS3形成時のガスフローを示す図面であり、図16は、図6のA−A部分および図13のB−B部分の飛行時間二次イオン質量分析計(TOF−SIMS)によるCN−強度(窒素濃度)分布を示すグラフである。
本実施の形態3は、上記実施の形態2の変形例であり、実施の形態2とは、第1電界緩和層ER1および第2電界緩和層ER2の形成方法が異なり、その他の部分は同様である。本実施の形態3では、第1電界緩和層ER1は第2層間絶縁膜INS2の形成工程後に、第2電界緩和層ER2は第3層間絶縁膜INS3の形成後に形成される。つまり、第2層間絶縁膜INS2を形成した後、第2層間絶縁膜INS2の表面から所定の深さに窒素のイオン打ち込みを実施することにより、第2層間絶縁膜INS2の表面より深い位置に第1電界緩和層ER1を形成するものである。第3層間絶縁膜INS3にも同様の方法を適用できる。
本実施の形態4は、上記実施の形態1の変形例であり、以下の相違点が有る。先ず、第1絶縁性バリヤ膜BR1が第1サブ絶縁性バリヤ膜BR11と第2サブ絶縁性バリヤ膜BR12とで構成されており、第2絶縁性バリヤ膜BR2が第1サブ絶縁性バリヤ膜BR21と第2サブ絶縁性バリヤ膜BR22とで構成されている。第2層間絶縁膜INS2内の第1電界緩和層ER1および第3電界緩和層INS3内の第2電界緩和層2は形成されていない。
(a)半導体基板を準備する工程、
(b)前記半導体基板上に、第1主面を有し、かつ所定の膜厚を有する層間絶縁膜を形成する工程、
(c)前記層間絶縁膜の前記第1主面に第1配線溝および第2配線溝を形成する工程、
(d)前記第1配線溝および第2配線溝内に選択的に銅膜を設け、第1配線および第2配線を形成する工程、
(e)前記第1配線、前記第2配線および前記層間絶縁膜の前記第1主面にアンモニアを含有するプラズマ処理を施す工程、
を有し、
前記工程(e)において、前記層間絶縁膜の前記第1主面にはダメージ層が形成され、前記ダメージ層の下方には電界緩和層が形成され、
前記ダメージ層および前記電界緩和層の窒素濃度は、前記層間絶縁膜の窒素濃度よりも大であり、前記電界緩和層の窒素濃度は前記ダメージ層の窒素濃度よりも大である、半導体装置の製造方法。
BR1,BR2 絶縁性バリヤ膜
BR11,BR12,BR21,BR22 サブ絶縁性バリヤ層
CU1,CU2 銅膜
CBR1,CBR2 導電性バリヤ膜
DM1,DM2 ダメージ層
ER1,ER2 電界緩和層
EST1,EST2 エッチングストッパ膜
INS1,INS2,INS3 層間絶縁膜
INS21,INS31,INS32 絶縁膜
M1W,M2W 配線
M1V,M2V プラグ電極
NCH,PCH チャネル領域
NG,PG ゲート電極
NGI,PGI ゲート絶縁膜
NSD,PSD ソース領域またはドレイン領域
NW N型ウエル領域
PR1,PR2,PR3,PR4 レジスト膜
PW P型ウエル領域
Qn N型MISFET
Qp P型MISFET
SUB P型半導体基板
SIL シリサイド膜
ST 素子分離膜
VG1,VG2 コンタクトホール
WG1,WG2 配線溝
Claims (20)
- 半導体基板と、
前記半導体基板上に形成され、主面を有する層間絶縁膜と、
前記層間絶縁膜内に埋め込まれ、互いに隣接する第1配線および第2配線と、
前記第1配線と前記第2配線との間に位置し、前記層間絶縁膜の前記主面に形成されたダメージ層と、
前記ダメージ層の下方において、前記層間絶縁膜に形成された電界緩和層と、
を有し、
前記第1配線と前記第2配線とは、主に銅膜からなり、
前記ダメージ層と前記電界緩和層とは、窒素を含む層であり、前記電界緩和層の窒素濃度は、前記ダメージ層の窒素濃度よりも大である、半導体装置。 - 請求項1記載の半導体装置において、
前記層間絶縁膜は、誘電率が3.0以下の絶縁膜からなる、半導体装置。 - 請求項2記載の半導体装置において、
前記層間絶縁膜は、SiCOH膜からなる、半導体装置。 - 請求項1記載の半導体装置において、
前記ダメージ層は、前記層間絶縁膜の前記主面から深さ4nmの範囲に存在する、半導体装置。 - 請求項1記載の半導体装置において、
前記電界緩和層は、窒素濃度のピーク領域を有する、半導体装置。 - 請求項5記載の半導体装置において、
前記窒素濃度のピーク領域は、前記層間絶縁膜の前記主面から5〜20nmの範囲に位置する、半導体装置。 - 請求項1記載の半導体装置において、
前記電界緩和層は、前記層間絶縁膜の前記主面を基準にして、前記第1配線の厚さの1/2より浅い位置に設けられている、半導体装置。 - 半導体基板と、
前記半導体基板上に形成され、第1主面を有する層間絶縁膜と、
前記層間絶縁膜内に埋め込まれ、互いに隣接する第1配線および第2配線と、
前記第1配線と前記第2配線との間に位置し、前記層間絶縁膜の前記第1主面に形成されたダメージ層と、
前記第1配線、前記第2配線およびダメージ層に接触し、前記第1配線、前記第2配線および前記層間絶縁膜を覆う絶縁性バリヤ膜と、
を有し、
前記第1配線と前記第2配線とは、主に銅膜からなり、
前記絶縁性バリヤ膜は、窒素を含有する絶縁膜であり、前記ダメージ層に接触する第1表面と前記第1表面と反対側の第2表面とを有し、前記絶縁性バリヤ膜は、前記第1表面の窒素濃度よりも高い窒素濃度を有する第1領域を有する、半導体装置。 - 請求項8記載の半導体装置において、
前記窒素濃度が高い第1領域は、前記第2表面側に位置する、半導体装置。 - 請求項8記載の半導体装置において、
前記絶縁性バリヤ膜の窒素濃度は、前記第1表面から前記第2表面に向かって増加している、半導体装置。 - 請求項8記載の半導体装置において、
前記層間絶縁膜は、誘電率が3.0以下の絶縁膜からなる、半導体装置。 - 請求項11記載の半導体装置において、
前記層間絶縁膜は、SiCOH膜からなる、半導体装置。 - 請求項8記載の半導体装置において、
前記ダメージ層の下方において、前記層間絶縁膜内に電界緩和層を有する、半導体装置。 - 請求項13記載の半導体装置において、
前記ダメージ層と前記電界緩和層とは、窒素を含む層であり、前記電界緩和層の窒素濃度は、前記ダメージ層の窒素濃度よりも大である、半導体装置。 - (a)半導体基板を準備する工程、
(b)前記半導体基板上に、第1主面を有し、かつ所定の膜厚を有する層間絶縁膜を形成する工程、
(c)前記層間絶縁膜の前記第1主面に第1配線溝および第2配線溝を形成する工程、
(d)前記第1配線溝および第2配線溝内に選択的に銅膜を設け、第1配線および第2配線を形成する工程、
(e)前記第1配線、前記第2配線および前記層間絶縁膜の前記第1主面にアンモニアを含有するプラズマ処理を施す工程、
を有し、
前記工程(b)において、前記層間絶縁膜には、前記第1主面より深い位置に電界緩和層が設けられており、
前記工程(e)において、前記層間絶縁膜の前記第1主面にはダメージ層が形成される、半導体装置の製造方法。 - 請求項15記載の半導体装置の製造方法において、
前記電界緩和層と前記ダメージ層は、前記層間絶縁膜よりも窒素濃度が大の層である、半導体装置の製造方法。 - 請求項16記載の半導体装置の製造方法において、
前記電界緩和層は、前記層間絶縁膜を形成後に、前記層間絶縁膜内に窒素をイオン打ち込みすることにより形成する、半導体装置の製造方法。 - 請求項16記載の半導体装置の製造方法において、
前記層間絶縁膜はSiCOH膜からなり、前記SiCOH膜は、有機シランガスおよび酸化ガスを用いたCVD法により形成し、
前記SiCOH膜形成工程の途中でアンモニアガスを添加することにより、前記SiCOH膜内に前記電界緩和層を形成する、半導体装置の製造方法。 - 請求項15記載の半導体装置の製造方法において、
前記層間絶縁膜はSiCOH膜からなり、前記SiCOH膜は、有機シランガスおよび酸化ガスを用いたCVD法により形成し、
前記SiCOH膜形成工程の途中で酸素系ガスの流量を増加することにより、前記SiCOH膜内に前記電界緩和層を形成する、半導体装置の製造方法。 - 請求項15記載の半導体装置の製造方法において、
前記工程(e)の後に、更に、
(f)前記層間絶縁膜上に、前記第1配線、前記第2配線および前記ダメージ層に接する第1表面と前記第1表面と反対側の第2表面を有する絶縁性バリヤ膜を形成する工程、
を有し、
前記絶縁性バリヤ膜の前記第2表面の窒素濃度は、前記第1表面の窒素濃度よりも大である、半導体装置の製造方法。
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KR20170124621A (ko) | 2011-12-20 | 2017-11-10 | 인텔 코포레이션 | 등각 저온 밀봉 유전체 확산 장벽들 |
JP6134727B2 (ja) * | 2013-11-08 | 2017-05-24 | ルネサスエレクトロニクス株式会社 | 半導体装置およびその製造方法 |
US9614045B2 (en) * | 2014-09-17 | 2017-04-04 | Infineon Technologies Ag | Method of processing a semiconductor device and chip package |
US9859154B2 (en) * | 2016-03-11 | 2018-01-02 | Taiwan Semiconductor Manufacturing Co., Ltd. | Structure and formation method of interconnect structure of semiconductor device |
US10269706B2 (en) * | 2016-07-26 | 2019-04-23 | Taiwan Semiconductor Manufacturing Co., Ltd. | Semiconductor device and manufacturing method thereof |
JP2018129481A (ja) | 2017-02-10 | 2018-08-16 | ルネサスエレクトロニクス株式会社 | 半導体装置 |
US10679936B2 (en) * | 2017-09-28 | 2020-06-09 | Taiwan Semiconductor Manufacturing Co., Ltd. | MIM structure |
US10347543B2 (en) * | 2017-11-13 | 2019-07-09 | Globalfoundries Inc. | FDSOI semiconductor device with contact enhancement layer and method of manufacturing |
KR102450580B1 (ko) * | 2017-12-22 | 2022-10-07 | 삼성전자주식회사 | 금속 배선 하부의 절연층 구조를 갖는 반도체 장치 |
JP7015218B2 (ja) * | 2018-06-28 | 2022-02-02 | ルネサスエレクトロニクス株式会社 | 半導体装置 |
DE102019120765B4 (de) * | 2018-09-27 | 2024-02-22 | Taiwan Semiconductor Manufacturing Co., Ltd. | Verfahren zum bilden eines halbleiterbauelements |
US11164954B2 (en) * | 2019-06-10 | 2021-11-02 | Globalfoundries U.S. Inc. | Gate capping layers of semiconductor devices |
US11699618B2 (en) * | 2020-01-24 | 2023-07-11 | Taiwan Semiconductor Manufacturing Co., Ltd. | Low-k dielectric damage prevention |
Citations (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2003229481A (ja) * | 2001-11-27 | 2003-08-15 | Nec Electronics Corp | 半導体装置及びその製造方法 |
JP2005302811A (ja) * | 2004-04-07 | 2005-10-27 | Tokyo Electron Ltd | 半導体装置の製造方法 |
JP2006128591A (ja) * | 2004-01-13 | 2006-05-18 | Tokyo Electron Ltd | 半導体装置の製造方法及び成膜システム |
JP2006525651A (ja) * | 2002-12-23 | 2006-11-09 | アドバンスト・マイクロ・ディバイシズ・インコーポレイテッド | low−k誘電体の最上部に反射防止特性を持つキャップ層の形成法 |
JP2010272826A (ja) * | 2009-05-25 | 2010-12-02 | Panasonic Corp | 半導体装置及びその製造方法 |
Family Cites Families (30)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP4200568B2 (ja) * | 1998-12-18 | 2008-12-24 | ソニー株式会社 | 電子装置およびその製造方法 |
US6472755B1 (en) | 1999-01-05 | 2002-10-29 | Advanced Micro Devices, Inc. | Semiconductor device comprising copper interconnects with reduced in-line copper diffusion |
KR100746895B1 (ko) * | 1999-08-10 | 2007-08-07 | 가부시키가이샤 히타치세이사쿠쇼 | 반도체 집적 회로 장치의 제조 방법 |
US6432812B1 (en) * | 2001-07-16 | 2002-08-13 | Lsi Logic Corporation | Method of coupling capacitance reduction |
JP2003142579A (ja) * | 2001-11-07 | 2003-05-16 | Hitachi Ltd | 半導体装置の製造方法および半導体装置 |
JP2003347299A (ja) * | 2002-05-24 | 2003-12-05 | Renesas Technology Corp | 半導体集積回路装置の製造方法 |
JP2004023008A (ja) * | 2002-06-20 | 2004-01-22 | Renesas Technology Corp | 半導体集積回路装置およびその製造方法 |
DE10260619B4 (de) | 2002-12-23 | 2011-02-24 | Globalfoundries Inc. | Verfahren zur Herstellung einer Deckschicht mit antireflektierenden Eigenschaften auf einem Dielektrikum mit kleinem ε |
JP4086673B2 (ja) * | 2003-02-04 | 2008-05-14 | Necエレクトロニクス株式会社 | 半導体装置及びその製造方法 |
KR100800639B1 (ko) | 2003-02-06 | 2008-02-01 | 동경 엘렉트론 주식회사 | 플라즈마 처리 방법, 반도체 기판 및 플라즈마 처리 장치 |
JP4454242B2 (ja) | 2003-03-25 | 2010-04-21 | 株式会社ルネサステクノロジ | 半導体装置およびその製造方法 |
US7276441B1 (en) * | 2003-04-15 | 2007-10-02 | Lsi Logic Corporation | Dielectric barrier layer for increasing electromigration lifetimes in copper interconnect structures |
DE10319136B4 (de) * | 2003-04-28 | 2008-06-12 | Advanced Micro Devices, Inc., Sunnyvale | Verfahren zur Herstellung einer Metallisierungsschicht mit einer mit Stickstoff angereicherten Barrierenschicht mit kleinem ε |
JP2005136152A (ja) * | 2003-10-30 | 2005-05-26 | Renesas Technology Corp | 半導体装置の製造方法 |
US7803705B2 (en) | 2004-01-13 | 2010-09-28 | Tokyo Electron Limited | Manufacturing method of semiconductor device and film deposition system |
US7223691B2 (en) * | 2004-10-14 | 2007-05-29 | International Business Machines Corporation | Method of forming low resistance and reliable via in inter-level dielectric interconnect |
DE102005052052B4 (de) * | 2005-10-31 | 2008-02-07 | Advanced Micro Devices, Inc., Sunnyvale | Ätzstoppschicht für Metallisierungsschicht mit verbesserter Haftung, Ätzselektivität und Dichtigkeit und Verfahren zur Herstellung eines dielektrischen Schichtstapels |
JP2007324536A (ja) | 2006-06-05 | 2007-12-13 | Renesas Technology Corp | 層間絶縁膜およびその製造方法、ならびに半導体装置 |
JP5016286B2 (ja) * | 2006-10-12 | 2012-09-05 | ローム株式会社 | 半導体装置および半導体装置の製造方法 |
JP2007005840A (ja) * | 2006-10-16 | 2007-01-11 | Renesas Technology Corp | 半導体集積回路装置の製造方法 |
JP5357401B2 (ja) * | 2007-03-22 | 2013-12-04 | ルネサスエレクトロニクス株式会社 | 半導体装置およびその製造方法 |
JP2009117743A (ja) * | 2007-11-09 | 2009-05-28 | Panasonic Corp | 半導体装置及びその製造方法 |
US7737029B2 (en) * | 2008-03-18 | 2010-06-15 | Samsung Electronics Co., Ltd. | Methods of forming metal interconnect structures on semiconductor substrates using oxygen-removing plasmas and interconnect structures formed thereby |
JP2010045161A (ja) * | 2008-08-12 | 2010-02-25 | Toshiba Corp | 半導体装置およびその製造方法 |
JP5238615B2 (ja) * | 2009-06-04 | 2013-07-17 | 株式会社東芝 | 半導体装置の製造方法 |
JP5326949B2 (ja) * | 2009-09-09 | 2013-10-30 | 株式会社日立製作所 | 半導体装置 |
JP2012038898A (ja) * | 2010-08-06 | 2012-02-23 | Renesas Electronics Corp | 半導体装置の製造方法および半導体装置 |
JP5665557B2 (ja) * | 2011-01-14 | 2015-02-04 | ルネサスエレクトロニクス株式会社 | 半導体装置および半導体装置の製造方法 |
JP5755471B2 (ja) * | 2011-03-10 | 2015-07-29 | ルネサスエレクトロニクス株式会社 | 半導体装置の製造方法 |
JP6134727B2 (ja) * | 2013-11-08 | 2017-05-24 | ルネサスエレクトロニクス株式会社 | 半導体装置およびその製造方法 |
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Patent Citations (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2003229481A (ja) * | 2001-11-27 | 2003-08-15 | Nec Electronics Corp | 半導体装置及びその製造方法 |
JP2006525651A (ja) * | 2002-12-23 | 2006-11-09 | アドバンスト・マイクロ・ディバイシズ・インコーポレイテッド | low−k誘電体の最上部に反射防止特性を持つキャップ層の形成法 |
JP2006128591A (ja) * | 2004-01-13 | 2006-05-18 | Tokyo Electron Ltd | 半導体装置の製造方法及び成膜システム |
JP2005302811A (ja) * | 2004-04-07 | 2005-10-27 | Tokyo Electron Ltd | 半導体装置の製造方法 |
JP2010272826A (ja) * | 2009-05-25 | 2010-12-02 | Panasonic Corp | 半導体装置及びその製造方法 |
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