TW201901902A - 半導體裝置 - Google Patents

半導體裝置 Download PDF

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Publication number
TW201901902A
TW201901902A TW107134158A TW107134158A TW201901902A TW 201901902 A TW201901902 A TW 201901902A TW 107134158 A TW107134158 A TW 107134158A TW 107134158 A TW107134158 A TW 107134158A TW 201901902 A TW201901902 A TW 201901902A
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Taiwan
Prior art keywords
insulating film
film
interlayer insulating
wiring
layer
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TW107134158A
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English (en)
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TWI669795B (zh
Inventor
宇佐美達矢
三浦幸男
土屋秀昭
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日商瑞薩電子股份有限公司
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Publication of TW201901902A publication Critical patent/TW201901902A/zh
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Publication of TWI669795B publication Critical patent/TWI669795B/zh

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    • H—ELECTRICITY
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    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/528—Geometry or layout of the interconnection structure
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    • H01L21/02074—Cleaning during device manufacture during, before or after processing of conductive layers, e.g. polysilicon or amorphous silicon layers the processing being a planarization of conductive layers
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    • H01L21/02126—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material containing Si, O, and at least one of H, N, C, F, or other non-metal elements, e.g. SiOC, SiOC:H or SiONC
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Abstract

本發明之半導體裝置包含：層間絕緣膜INS2；鄰接之Cu配線M1W，其形成於層間絕緣膜INS2內；及絕緣性障壁膜BR1，其接觸於層間絕緣膜INS2之表面與Cu配線M1W之表面，且覆蓋層間絕緣膜INS2與Cu配線M1W。且，於鄰接之Cu配線M1W間，層間絕緣膜INS2於其表面具有損傷層DM1，且於較損傷層DM1更深之位置，具有含有較損傷層DM1之氮濃度更高之氮濃度之電場緩和層ER1。

Description

半導體裝置
本發明係關於半導體裝置及其製造方法，例如可較好地利用於具備Cu配線之半導體裝置及其製造方法。
於近年來之半導體裝置中，為高速動作、低耗電等，而必須應用Cu(銅)配線。Cu配線係藉由使用鑲嵌(Damascene)法，於半導體基板上之層間絕緣膜形成配線槽後，於該配線槽之內部及層間絕緣膜上堆積Cu(銅)膜，接著使用化學機械研磨(CMP：Chemical Mechanical Polishing)法於配線槽內選擇性殘留Cu膜而形成。於層間絕緣膜，使用氧化矽膜等。 因構成Cu配線之Cu係例如與如Al(鋁)之配線材料相比，易擴散於氧化矽膜等之層間絕緣膜中，故Cu配線之底面及側面係以TiN(氮化鈦)膜等之導電性障壁膜覆蓋。又，Cu配線之表面係與鄰接之層間絕緣膜之表面一同以絕緣性障壁膜覆蓋。 於此種Cu配線構造中，Cu離子於層間絕緣膜與絕緣性障壁膜之界面移動，藉此產生Cu配線之TDDB(Time Dependence on Dielectric Breakdown：時間相依介電質崩潰)。尤其，若於Cu-CMP後Cu表面被氧化成CuO，則Cu易離子化，且TDDB劣化。為使該Cu配線之TDDB特性提高，已知有一種技術，其係對Cu配線及層間絕緣膜之表面實施氨(NH3)電漿處理，將Cu配線表面之CuO還原成Cu，並於其後形成絕緣性障壁膜。 又，作為層間絕緣膜，為降低配線間電容，而研究低介電常數之絕緣膜、例如SiCOH等之使用。 於“Effective Cu Surface Pre-treatment for High-reliable 22nm-node Cu Dual Damascene Interconnects with High Plasma resistant Ultra Low-k Dielectric(k=2.2)”(非專利文獻1)，揭示有對形成於低介電常數之絕緣膜之Cu配線實施氨電漿處理之情形。又，揭示有藉由氨電漿處理，於低介電常數之層間絕緣膜表面形成如氧化膜之介電常數較高之損傷層，且RC特性或可靠性降低之情形。 [先前技術文獻] [非專利文獻] [非專利文獻1]F.Ito et al., “Effective Cu Surface Pre-treatment for High-reliable 22nm-node Cu Dual Damascene Interconnects with High Plasma resistant Ultra Low-k Dielectric(k=2.2)” Advanced Metalization Conference October 5-7, 2010
[發明所欲解決之問題] 本發明者對作為層間絕緣膜使用低介電常數之絕緣膜之Cu配線進行研究，發現如下問題點。 隨著半導體裝置之微細化發展，Cu配線間空間變小，另一方面，電源電壓保持大致一定，施加於Cu配線間之層間絕緣膜之電場強度有變大之傾向。又，Cu配線依存於其製造方法，於膜厚方向具有錐形形狀，施加於鄰接之Cu配線之上端部間之電場為最高。即，可以說層間絕緣膜與絕緣性障壁膜之界面係最容易引起TDDB破壞(TDDB壽命下降)之部位。 再者，藉由CMP處理後之氨電漿處理，低介電常數之層間絕緣膜之表面氧化及氮化而形成損傷層時，因損傷層部分之介電常數較層間絕緣膜之介電常數要高，故電場容易集中於損傷層部分，而存在Cu配線間之TDDB壽命下降(惡化)之問題。 其他問題與新穎之特徵係根據本說明書之記述及附加圖式得以明確。 [解決問題之技術手段] 根據一實施形態，半導體裝置具有：層間絕緣膜；鄰接之Cu配線，其形成於層間絕緣膜內；及絕緣性障壁膜，其接觸於層間絕緣膜之表面與Cu配線之表面，且覆蓋層間絕緣膜與Cu配線。且，於鄰接之Cu配線間，層間絕緣膜於其表面具有損傷層，且於較損傷層更深之位置，具有含有較損傷層之氮濃度更高之氮濃度之電場緩和層。 [發明之效果] 根據一實施形態，可提高具備Cu配線之半導體裝置之TDDB壽命。
以下，基於圖式詳細說明實施形態。另，於用以說明實施形態之全圖中，對具有相同功能之構件標註相同符號，且省略其重複之說明。又，於以下之實施形態中，除特別必要時以外，原則上不重複相同或同樣部分之說明。 又，於實施形態所使用之圖式中，剖面圖亦存在為便於觀察圖式而省略陰影線之情形。又，俯視圖亦存在為便於觀察圖式而標註陰影線之情形。 (實施形態1) 圖1係顯示本實施形態之半導體裝置之剖面構造之主要部分剖面圖。 於包含矽之P型半導體基板SUB之主表面(表面)，形成有複數個P型井區域PW與複數個N型井區域NW。於P型井區域PW內，形成N型MISFET(Metal Insulator Semiconductor Field Effect Transistor：金屬絕緣半導體場效電晶體) Qn(以下記述為N型MISFETQn)，於N型井區域NW內形成P型MISFET Qp(以下記述為P型MISFETQp)。於半導體基板SUB之表面，部分形成有以氧化矽膜等之絕緣膜構成之元件分離膜(元件分離區域)ST。元件分離膜ST係於P型井區域PW內及N型井區域NW內，規定N型MISFET形成區域及P型MISFEST形成區域。即，於俯視下，於P型井區域PW內之元件分離膜ST所包圍之區域，形成1個或複數個N型MISFET。又，於俯視下，於N型井區域NW內之元件分離膜ST所包圍之區域，形成1個或複數個P型MISFETQp。N型MISFETQn係包含接觸於元件分離膜ST之N型之源極區域NSD及N型之汲極區域NSD、源極區域NSD與汲極區域NSD之間之通道形成區域NCH、及介隔閘極絕緣膜NGI形成於通道形成區域NCH上之閘極電極NG。於N型之源極區域NSD、N型之汲極區域NSD及閘極電極NG之表面形成有矽化物膜SIL。P型MISFETQp係包含接觸於元件分離膜ST之P型之源極區域PSD及P型之汲極區域PSD、源極區域PSD與汲極區域PSD之間之通道形成區域PCH、及介隔閘極絕緣膜PGI形成於通道形成區域PCH上之閘極電極PG。於P型之源極區域PSD、P型之汲極區域PSD及閘極電極PG之表面形成有矽化物膜SIL。 N型MISFETQn、P型MISFETQp及元件分離膜ST係以包含氮化矽膜之絕緣膜即第1蝕刻阻止膜EST1覆蓋。再者，於第1蝕刻阻止膜EST1上，形成有絕緣膜即第1層間絕緣膜INS1，第1層間絕緣膜INS1係包含BP(Boron、Phosphorus：硼、磷)-TEOS膜。於第1蝕刻阻止膜EST1及第1層間絕緣膜INS1，形成有複數個第1接觸孔VG1，於第1接觸孔VG1內設置有金屬導體膜即第1插塞電極M1V。第1插塞電極M1V係與N型MISFETQn之源極區域NSD及汲極區域NSD、以及P型MISFETQp之源極區域PSD及汲極區域PSD電性連接。第1插塞電極M1V係以氮化鈦膜(TiN)與鎢膜(W)之積層構造構成。第1蝕刻阻止膜EST1係於第1層間絕緣膜INS1形成第1接觸孔VG1時，作為蝕刻阻止層發揮功能。第1接觸孔VG1形成時之蝕刻係進行以第1層間絕緣膜INS1之蝕刻率相對於第1蝕刻阻止膜EST1之蝕刻率為較大之條件用以於第1層間絕緣膜INS1形成第1接觸孔VG1之蝕刻。繼而，藉由實施用以於相對於第1層間絕緣膜INS1膜厚較小之第1蝕刻阻止層EST1形成第1接觸孔VG1之蝕刻，可降低半導體基板SUB之削減。 於第1層間絕緣膜INS1及第1插塞電極M1V上，依序形成有絕緣膜之第2蝕刻阻止膜EST2與絕緣膜之第2層間絕緣膜INS2。第2蝕刻阻止膜EST2包含氮化矽膜，第2層間絕緣膜INS2係例如以介電常數為3.0以下之Low-k絕緣膜構成。第2層間絕緣膜INS2具體為SiCOH，作為其以外之膜，為有機聚合物膜(聚伸芳基、苯幷環丁烯、聚醯亞胺等)、派瑞林(註冊商標)或BCN(氮化硼碳)膜等。於第2蝕刻阻止膜EST2與第2層間絕緣膜INS2，設置有複數個第1配線槽WG1，於第1配線槽WG1內，形成有包含金屬導體膜之第1配線M1W。第1配線M1W係包含鈦(Ti)、氮化鈦(TiN)膜、鉭(Ta)膜及氮化鉭(TaN)膜之1個或複數個之積層膜與銅(Cu)膜之積層構造之銅(Cu)配線。銅膜係將銅作為主成分，亦可包含鋁(Al)、錳(Mn)或鈀(Pd)等添加物。鈦(Ti)、氮化鈦(TiN)膜、鉭(Ta)膜及氮化鉭(TaN)膜之1個或複數個之積層膜係位於銅(Cu)膜與第2層間絕緣膜INS2之間，具有防止銅(Cu)擴散於第2層間絕緣膜INS2內之作用。即，為上述之導電性障壁膜。第1配線M1W係電性連接於第1插塞電極M1V。 以覆蓋第1配線M1W及第2層間絕緣膜INS2之方式，依序形成有絕緣膜之第1絕緣性障壁膜BR1、及絕緣膜之第3層間絕緣膜INS3。第1絕緣性障壁膜BR1係包含氮化矽膜或氮化碳化矽薄膜(SiCN薄膜)或該等之積層膜。第1絕緣性障壁膜BR1具有防止構成第1配線M1W之銅(Cu)擴散於第3層間絕緣膜INS3內之作用。即，為上述之絕緣性障壁膜。又，第3層間絕緣膜INS3係以與第2層間絕緣膜INS2相同之材料構成，例如包含SiCOH。 於第3層間絕緣膜INS3，設置有複數個第2配線槽WG2，於第2配線槽WG2內，形成有包含金屬導體膜之第2配線M2W。以與第1配線槽WG1連接之方式，於第3層間絕緣膜INS3及第1障壁膜BR1，形成有第2接觸孔VG2，於第2接觸孔VG2內，設置有包含金屬導體膜之第2插塞電極M2V。第2配線M2W及第2插塞電極M2V係以包含鈦(Ti)、氮化鈦(TiN)膜、鉭(Ta)膜及氮化鉭(TaN)膜之一個或複數個之積層膜與銅(Cu)膜之積層構造之銅(Cu)配線一體構成。鈦(Ti)、氮化鈦(TiN)膜、鉭(Ta)膜及氮化鉭(TaN)膜之一個或複數個之積層膜係位於銅(Cu)膜與第3層間絕緣膜INS3之間，具有防止銅(Cu)擴散於第3層間絕緣膜INS3內之作用。即，為上述之導電性障壁膜。銅膜係將銅作為主成分，亦可包含鋁(Al)、錳(Mn)或鈀(Pd)等添加物。第2配線M2W係經由第2插塞電極M2V電性連接於第1配線M1W。以覆蓋第2配線M2W及第3層間絕緣膜INS3之方式，形成有絕緣膜之第2絕緣性障壁膜BR2。第2絕緣性障壁膜BR2係包含氮化矽膜及氮化碳化矽薄膜(SiCN薄膜)之單層膜或積層膜等。 於本實施形態中，僅顯示了第1層配線即第1配線M1W及第2層配線即第2配線M2W，亦可於第2配線M2W上進而形成配線。 以下，於圖1中，利用虛線所包圍之部分說明本實施形態。 圖2至圖6及圖8至圖13係本實施形態之半導體裝置之製造步驟中之主要部分剖面圖。圖7係SiN/SiCOH積層構造之飛行時間型二次離子質譜法(TOF－SIMS：Time Of Flight Secondary Ion Mass Spectrometry)之CN-強度之深度分佈圖，圖14係顯示TOF-SIMS之SiCOH膜之CN-強度之整體與SiN之附近之SiCOH表層部之比與實際之同層配線間之TDDB壽命之關係之圖表。以下，亦一面參照圖1一面說明本實施形態之半導體裝置之製法。圖2係說明第2層間絕緣膜INS2及第1絕緣膜INS21之形成步驟之圖式。準備形成有N型MISFETQn及P型MISFETQp之半導體基板SUB，且以覆蓋N型MISFETQn及P型MISFETQp之方式，於半導體基板SUB上形成包含絕緣膜之第1層間絕緣膜INS1。其次，以露出N型MISFETQn之源極區域NSD及汲極區域NSD、以及P型MISFETQp之源極區域PSD及汲極區域PSD之方式，於第1層間絕緣膜INS1形成第1接觸孔VG1。繼而，於第1接觸孔VG1內形成第1插塞電極M1V。接著，如圖2所示，於第1插塞電極M1V及第1層間絕緣膜INS1上，依序形成包含絕緣膜之第2蝕刻阻止層EST2、包含絕緣膜之第2層間絕緣膜INS2、及包含絕緣膜之第1絕緣膜INS21。構成第2層間絕緣膜INS2之SiCOH膜係可藉由使用有機矽烷氣體(3MS：三甲基矽烷，4MS：四甲基矽烷，1MS：單甲基矽烷，2MS：二甲基矽烷)及氧化氣體(O2、N2O、CO、CO2等)之CVD法形成。第1絕緣膜INS21係較第2層間絕緣膜INS2介電常數要高且機械性強度大之膜，例如可使用較氧化矽膜或第2層間絕緣膜INS2介電常數高且加工耐性優秀之SiCOH膜。第1絕緣膜INS21之膜厚小於第2層間絕緣膜INS2之膜厚。 圖3係說明第1配線槽WG1之形成步驟之圖式。於第1絕緣膜INS21上形成包含具有與第1配線M1W之圖案對應之開口部之絕緣膜之第1抗蝕劑膜PR1。將第1抗蝕劑膜PR1作為遮罩而對第1絕緣膜INS21、第2層間絕緣膜INS2實施乾蝕刻，形成第1配線槽WG1。該乾蝕刻係對第2蝕刻阻止膜EST2，以第2層間絕緣膜INS2及第1絕緣膜INS21之蝕刻率較高(大)之條件實施。第1配線槽WG1不僅形成於第2層間絕緣膜INS2，亦形成於第1絕緣膜INS21。又，第1配線槽WG1之剖面形狀成為第1配線槽WG1之上部之開口徑寬於第1配線槽WG1之底部之開口徑之錐形形狀。即，鄰接之第1配線槽WG1間之第1絕緣膜INS21及第2層間絕緣膜INS2之寬度係成為上部較底部狹窄之形狀。 圖4係說明第1配線M1W之形成步驟之圖式。首先，除去第1抗蝕劑膜PR1，其後，藉由全面蝕刻將第2蝕刻阻止膜EST2進行蝕刻，露出第1插塞電極M1V之上表面。其後，於第1配線槽WG1內依序形成導電性膜之第1導電性障壁膜CBR1及導電性膜之第1銅膜CU1後，對半導體基板SUB之表面實施CMP處理。且，僅於第1配線槽WG1內選擇性殘留第1導電性障壁膜CBR1及第1銅膜CU1，且除去第2層間絕緣膜INS2上之第1導電性障壁膜CBR1及第1銅模CU1，藉此形成第1配線M1W。於該CMP處理中，亦除去第1絕緣膜INS21，獲得圖4所示之構造。由於藉由於鄰接之第1配線M1W間僅殘留第2層間絕緣膜INS2，鄰接之第1配線M1W間藉由Low-k絕緣膜電性分離，故可降低第1配線M1W間之電容。 圖5係說明氨電漿處理之步驟之圖式。於第1配線M1W及第2層間絕緣膜INS2之表面實施包含氨(NH3)氣之電漿處理。氨電漿處理係使用NH3氣體，以壓力：1.0~8.0 Torr、高頻功率：50 w~500 w、時間：3 Sec~100 Sec之條件實施。亦可於NH3氣體中添加N2氣體。藉由氨電漿處理，可於CMP處理中除去形成於構成第1配線M1W之第1銅膜CU1之表面之氧化膜(CuO)，以及對第2層間絕緣膜INS2之表面進行改質(例如，埋設懸掛鍵)。因此，可提高下一個步驟所形成之第1絕緣性障壁膜BR1與第1配線M1W之接著性(密著性)。但，因以Low-k膜構成第2層間絕緣膜INS2，故藉由該氨電漿處理，於第2層間絕緣膜INS2之表面形成第1損傷層DM1。第1損傷層DM1係形成於距第2層間絕緣膜INS2之表面深4 nm之範圍。第1損傷層DM1係構成第2層間絕緣膜INS2之SiCOH膜經氮化之膜。於本實施形態中，藉由氨電漿處理，而於第1損傷層DM1之下部形成第1電場緩和層ER1。第1電場緩和層ER1亦為構成第2層間絕緣膜INS2之SiCOH膜經氮化之膜。即，第1損傷層DM1與第1電場緩和層ER1係氮濃度較第2層間絕緣膜INS2更高之區域。於圖5中，為便於理解，分區域顯示第1損傷層DM1與第1電場緩和層ER1，但實際上兩者為一體。 圖6係說明第1絕緣性障壁膜BR1之形成步驟之圖式。以覆蓋藉由氨電漿處理除去氧化膜(CuO)之第1配線M1W表面及第2層間絕緣膜INS2表面之方式，形成包含絕緣膜之第1絕緣性障壁膜BR1。 圖7係顯示設想圖6之A-A部分之TOF-SIMS之CN-強度(氮濃度)分佈之圖表。藉由TOF-SIMS法，分析第1絕緣性障壁膜BR1至第2層間絕緣膜INS2之特定深度之結果，使用CN-強度表示氮濃度。第2層間絕緣膜INS2之深度方向之氮濃度係於較表面要深之位置具有濃度峰值。濃度峰值係位於距第2層間絕緣膜INS2之表面5 nm~20 nm之範圍。第2層間絕緣膜INS2之表面部分(0~4 nm)為第1損傷層DM1，具有較表面部分之氮濃度要高之氮濃度之區域為第1電場緩和層ER1。於第1電場緩和層ER1，存在有氮濃度逐漸增加之區域、氮濃度之峰值區域、及氮濃度逐漸減少之區域。第1電場緩和層ER1之氮濃度較第1損傷層DM1之氮濃度要高。換言之，第1電場緩和層ER1之介電常數較第1損傷層DM1之介電常數要高。如此，藉由於鄰接之第1配線M1W間，於較第2層間絕緣膜INS2之表面(上表面)要深之位置，設置具有較表面之介電常數更高之介電常數之區域(層)，可緩和第2層間絕緣膜INS2之表面之電場。其結果，可提高鄰接之第1配線M1W間之TDDB特性(壽命)。由於若第1電場緩和層ER1距離第2層間絕緣膜INS2之表面過遠，則電場緩和效果減少，故而第1電場緩和層ER1之氮濃度峰值位置較好為較第1配線M1W之厚度之1/2更淺者。 圖8係說明第3層間絕緣膜INS3、第2絕緣膜INS31及第2接觸孔VG2之形成步驟之圖式。於第1絕緣性障壁膜BR1上，依序形成第3層間絕緣膜INS3、第2絕緣膜INS31。第3層間絕緣膜INS3及第2絕緣膜INS31係以與第2層間絕緣膜INS2及第1絕緣膜INS21相同之膜構成。其次，於第2絕緣膜INS31上，形成包含具有與第2接觸孔VG2對應之開口之絕緣膜之第2抗蝕劑膜PR2。如圖8所示，將該第2抗蝕劑膜PR2作為遮罩使用，對第2絕緣膜INS31、第3層間絕緣膜INS3實施乾蝕刻，形成第2接觸孔VG2。於第1絕緣性障壁膜BR1上阻止蝕刻。因此，於第2接觸孔VG2之底部殘留第1絕緣性障壁膜BR1。 其次，圖9係說明包含用以形成第2配線槽WG2之絕緣膜之第4抗蝕劑膜PR4之形成步驟之圖式。於除去第2抗蝕劑膜PR2後，於第2接觸孔VG2內及第2絕緣膜INS31上形成第3抗蝕劑膜PR3。於第3抗蝕劑膜PR3上，形成第3絕緣膜INS32及包含絕緣膜之防反射膜BARC。第3絕緣膜INS32係包含氧化矽膜，藉由低溫CVD法形成。其次，於防反射膜BARC上，形成具有與第2配線槽WG2對應之開口之第4抗蝕劑膜PR4。 圖10係說明形成第2配線槽WG2之步驟之圖式。將第4抗蝕劑膜PR4作為遮罩，對第2絕緣膜INS31及第3層間絕緣膜INS3實施乾蝕刻，形成第2配線槽WG2。此時形成於較第3抗蝕劑膜PR3更上方之第3絕緣膜INS32、防反射膜BARC及第4抗蝕劑膜PR4係同時被除去，如圖10所示，於第2配線槽WG2之周圍及第2接觸孔VG2內殘留第3抗蝕劑膜PR3。 圖11係說明除去第1障壁膜BR1之步驟之圖式。首先，除去殘留於第2配線槽WG2之周圍及第2接觸孔VG2內之第3抗蝕劑膜PR3，其後，為清除BR1之開口部，而實施全面蝕刻，藉此，如圖11所示，露出第1配線M1W之表面。於該全面蝕刻之步驟中，第2絕緣膜31亦受蝕刻而變薄。 圖12係說明形成第2配線M2W之步驟之圖式。於第2接觸孔VG2及第2配線槽WG2內依序形成導電性膜之第2導電性障壁膜CBR2及導電性膜之第2銅膜CU2後，對第2銅膜CU2之表面實施CMP處理。且，僅於第2接觸孔VG2內及第2配線槽WG2內選擇性殘留第2導電性障壁膜CBR2及第2銅膜CU2，並形成第2配線M2W。於該CMP處理中，亦除去第2絕緣膜INS31，露出第3層間絕緣膜INS3之表面，藉此，第2配線M2W間係藉由Low-k絕緣膜而電性分離，故而可降低第2配線M2W間之電容。 圖13係說明氨電漿處理之步驟與第2絕緣性障壁膜BR2之形成步驟之圖式。於第2配線M2W及第3層間絕緣膜INS3之表面，實施含有氨(NH3)氣之電漿處理。氨電漿處理之條件與第1配線M1W之情形相同。藉由該氨電漿處理，於第3層間絕緣膜INS3之表面形成第2損傷層DM2。第2損傷層DM2係形成於距第3層間絕緣膜INS3之表面深度4 nm之範圍。第2損傷層DM2係構成第3層間絕緣膜INS3之SiCOH膜被氮化之膜。於本實施形態中，藉由氨電漿處理，於第2損傷層DM2之下部形成第2電場緩和層ER2。第2電場緩和層ER2亦為構成第3層間絕緣膜INS3之SiCOH膜被氮化之膜。即，第2損傷層DM2與第2電場緩和層ER2係較第3層間絕緣膜INS3氮濃度更高之區域。於圖13中，為便於理解，分區域顯示第2損傷層DM2與第2電場緩和層ER2，實際上，兩者為一體。其次，以覆蓋第3層間絕緣膜INS3及第2配線M2W之方式形成包含絕緣膜之第2絕緣性障壁膜BR2，獲得圖13之構造。圖13之B-B部分之氮濃度分佈係與圖7所示之圖表相同。因第2電場緩和層ER2包含與第1電場緩和層ER1相同之構成，故第2電場緩和層ER2係發揮與第1電場緩和層ER1相同之效果者。因冗長而省略重複說明，圖7之說明段落之記述係可將第2層間絕緣膜INS2、第1損傷層DM1、第1電場緩和層ER1、及第1配線M1W置換成第3層間絕緣膜INS3、第2損傷層DM2、第2電場緩和層ER2、及第2配線M2W進行理解。 圖14係說明本實施形態之效果之圖表。圖14係顯示構成層間絕緣膜之SiCOH膜之內部與表面之CN-強度比(氮濃度比)與TDDB壽命之關係。若CN-強度比為1以上，則TDDB壽命提高1位數以上。即，於層間絕緣膜之內部，藉由設置具有較表面之氮濃度要高之氮濃度之層，TDDB壽命提高1位數以上。換言之，藉由設置具有較第1損傷層DM1之氮濃度要高之氮濃度之第1電場緩和層ER1，鄰接之第1配線M1W間之TDDB壽命提高1位數以上。同樣，藉由設置第2電場緩和層ER2，鄰接之第2配線M2W間之TDDB壽命提高1位數以上。 (實施形態2) 本實施形態2係上述實施形態1之變化例，與實施形態1不同的是第1電場緩和層ER1及第2電場緩和層ER2之形成方法與氨電漿處理之條件，其他部分相同。於本實施形態2中，第1電場緩和層ER1係於第2層間絕緣膜INS2之形成步驟中形成，第2電場緩和層ER2係於第3層間絕緣膜INS3之形成中形成。因此，於氨電漿處理步驟中，形成第1損傷層DM1及第2損傷層DM2，不形成第1電場緩和層ER1及第2電場緩和層ER2。圖15係顯示第2層間絕緣膜INS2及第3層間絕緣膜INS3形成時之氣體流量之圖式，圖16係顯示圖6之A-A部分及圖13之B-B部分之飛行時間二次離子質譜儀(TOF-SIMS)之CN-強度(氮濃度)分佈之圖表。 構成第2層間絕緣膜INS2之SiCOH膜係藉由使用有機矽烷氣體(3MS：三甲基矽烷，4MS：四甲基矽烷，1MS：單甲基矽烷，2MS：二甲基矽烷)及氧化氣體(O2、N2O、CO、CO2等)之CVD法形成。根據本實施形態2，特徵點在於：於特定時序添加含氮之氣體(N2、NH3等)。其他CVD條件為300~400℃之範圍、壓力為1.0~8.0 Torr、高頻功率為100 W~500 W之範圍。如圖15所示，於穩定之壓力下，流通有機矽烷氣體、氧氣(O2)，同時接通電力。於CVD成長之後半添加氨(NH3)氣，且緩慢提高流量，達到設定值後緩慢下降至0。其後，切斷有機矽烷氣體、氧氣(O2)，同時切斷電力。藉由實施如氨(NH3)氣之上述般之流量，可將膜中之氮濃度設為階度狀。藉由此種製法，可於較第2層間絕緣膜INS2之表面更深之位置形成第1電場緩和層ER1。藉由將該製法亦應用於第3層間絕緣膜INS3，可於第3層間絕緣膜INS3形成時，於較第3層間絕緣膜INS3之表面更深之位置形成第2電場緩和層ER2。對第2層間絕緣膜INS2及第3層間絕緣膜INS3之表面之氨電漿處理之條件係與實施形態1不同。氨電漿處理所產生之第1損傷層DM1及第2損傷層DM2較好為將氮濃度設為小於形成第2層間絕緣膜INS2及第3層間絕緣膜INS3時之電場緩和層ER1、ER2。例如，較理想為於氨電漿處理時添加氫氣。 根據本實施形態2，可實現與實施形態1之圖6及圖13所說明之構造相同之構造。其中，於圖16顯示藉由本實施形態2獲得之圖6之A-A部分及圖13之B-B部分之CN-強度(氮濃度)。例如，以圖6之A-A部分為例進行說明，圖13之B-B部分亦獲得相同之效果。與實施形態1之情形相同，於第1電場緩和層ER1，存在氮濃度逐漸增加之區域、氮濃度之峰值之區域、及氮濃度逐漸減少之區域。第1電場緩和層ER1之氮濃度較第1損傷層DM1之氮濃度要高。換言之，第1電場緩和層ER1之介電常數較第1損傷層DM1之介電常數要高。 因以與第1損傷層DM1不同之步驟形成第1電場緩和層ER1，而可降低第2層間絕緣膜INS2之表面之氨電漿處理造成之損傷，故與實施形態1相比，可提高鄰接之第1配線M1W間之TDDB壽命。又，容易控制第2層間絕緣膜INS2內之第1電場緩和層ER1之位置、即氮濃度峰值。氮濃度於較第1絕緣性障壁膜BR1與第2層間絕緣膜INS2界面更深處具有峰值係指該處介電常數變高，電場不會集中於第1絕緣性障壁膜BR1與第2層間絕緣膜INS2界面。結果，可改善配線間TDDB。 圖17係顯示本實施形態2之第2層間絕緣膜INS2之形成方法之變化例即氣體流量之圖式。亦可應用於第3層間絕緣膜INS3。特徵點在於：取代添加氨氣，使O2氣體之流量變化。如圖17所示，於穩定之壓力下流通機矽烷氣體、氧(O2)氣，同時施加高頻功率。於CVD成長之後半進而緩慢提高氧(O2)氣流量，達到設定值後緩慢下降至原設定值。其後，與有機矽烷氣體、氧(O2)氣同時切斷電力。藉由實施如上所述之流量，可將膜中之氧濃度設成階度狀。藉由此種製法，可於較第2層間絕緣膜INS2之表面更深之位置形成第1電場緩和層ER1。該製法亦可應用於第3層間絕緣膜INS3，其結果，可形成具有實施形態1之圖13之構造之半導體裝置。其中，與實施形態1不同點係第1電場緩和層ER1以具有較第2層間絕緣膜INS2之氧濃度更高濃度之氧濃度之層構成。因第1電場緩和層ER1之介電常數較第2層間絕緣膜INS2之介電常數要高，故藉由於較第2層間絕緣膜INS2之表面更深之位置配置具有較第2層間絕緣膜INS2之介電常數要高之介電常數之第1電場緩和層ER1，可緩和鄰接之第1配線M1W間之第2層間絕緣膜INS2之表面之電場。其結果，可提高鄰接之第1配線M1W間之TDDB壽命。第1電場緩和層ER1之氧濃度峰值位置較好為較第1配線M1W之厚度之1/2更淺。第2電場緩和層ER2之氧濃度峰值位置亦較好為較第2配線M2W之厚度之1/2更淺。 (實施形態3) 本實施形態3係上述實施形態2之變化例，與實施形態2不同之處在於第1電場緩和層ER1及第2電場緩和層ER2之形成方法，其他部分相同。於本實施形態3中，第1電場緩和層ER1係於第2層間絕緣膜INS2之形成步驟後形成，第2電場緩和層ER2係於第3層間絕緣膜INS3之形成後形成。即，於形成第2層間絕緣膜INS2後，藉由於距第2層間絕緣膜INS2之表面特定深度實施氮之離子植入，而於較第2層間絕緣膜INS2之表面更深之位置形成第1電場緩和層ER1。對第3層間絕緣膜INS3亦可應用相同之方法。 根據本實施形態3，可實現與實施形態1之圖6及圖13所說明之構造相同之構造。圖18係顯示圖6之A-A部分及圖13之B-B部分之飛行時間二次離子質譜儀(TOF-SIMS)之CN-強度(氮濃度)分佈之圖表。例如，於較第2層間絕緣膜INS2之表面之第1損傷層DM1更深之位置，存在有具有較第1損傷層DM1之氮濃度更高之氮濃度之第1電場緩和層ER1。於第1電場緩和層ER1內存在氮濃度之峰值部分。與實施形態2相比，有氮元素之深度方向與濃度控制優秀之優點。圖13之B-B部分亦可獲得相同之效果。 (實施形態4) 本實施形態4係上述實施形態1之變化例，具有以下不同點。首先，將第1絕緣性障壁膜BR1以第1次絕緣性障壁膜BR11與第2次絕緣性障壁膜BR12構成，將第2絕緣性障壁膜BR2以第1次絕緣性障壁膜BR21與第2次絕緣性障壁膜BR22構成。未形成第2層間絕緣膜INS2內之第1電場緩和層ER1及第3電場緩和層INS3內之第2電場緩和層2。 圖19係本實施形態4之半導體裝置之主要部分剖面構造。使用覆蓋第1配線M1W之第1絕緣性障壁膜BR1進行說明。第1絕緣性障壁膜BR1係以覆蓋第1配線M1W之第1次絕緣性障壁層BR11、與形成於第1次絕緣性障壁層BR11上之第2次絕緣性障壁層BR12構成。第2次絕緣性障壁層BR12具有較第1次絕緣性障壁層BR11之氮濃度要高之氮濃度。尤其，第2次絕緣性障壁層BR12具有較第1次絕緣性障壁層BR11之下表面(與第1配線M1W之界面)之氮濃度要高之氮濃度。於圖19中，為便於理解，分區域顯示第1次絕緣性障壁層BR11與第2次絕緣性障壁層BR12，實際上，兩者為一體。 圖20係顯示圖19之A-A部分之飛行時間二次離子質譜儀(TOF-SIMS)之CN-強度(氮濃度)分佈之圖表。與位於第1配線M1W間之第2層間絕緣膜INS2及形成於其上之第1絕緣性障壁膜BR1之界面之氮濃度相比，自界面離開之位置上之第1絕緣性障壁膜BR1之氮濃度較高。即，於自界面離開之位置存在第2次絕緣性障壁層BR12。第1絕緣性障壁膜BR1之氮濃度係隨著自第2層間絕緣膜INS2與形成於其上之第1絕緣性障壁膜BR1之界面離開而增加。 第1絕緣性障壁膜BR1係例如使用SiCN膜。SiCN膜係以例如CVD法形成，於溫度為300~400℃之範圍、壓力為1.0~8.0 Torr、高頻功率為50 W~1000 W之範圍內使用。氣體係使用有機矽烷、SiH4、氨(NH3)、CO、CO2、N2O等。圖21係使用有機矽烷氣體與氨(NH3)氣形成構成第1絕緣性障壁膜BR1之SiCN膜時之氣體流量圖。於穩定之壓力下，流通有機矽烷氣體、氨(NH3)氣，同時接通電力。於CVD成長之最後，對氨(NH3)氣進而緩慢提高原流量，達到設定值後緩慢下降，設為原設定值。其後，同時切斷有機矽烷氣體、氨(NH3)氣、及電力。藉由實施如上述之氨(NH3)氣流量，可將第1絕緣性障壁膜BR1中之氮濃度設成階度狀。 藉由與位於第1配線M1W間之第2層間絕緣膜INS2與形成於其上之第1絕緣性障壁膜BR1之界面之氮濃度相比，使自界面離開之位置上之第1絕緣性障壁膜BR1之氮濃度更高，可提高鄰接之第1配線M1W間之TDDB壽命。此係因為於自界面離開之位置，於第1絕緣性障壁膜BR1設置氮濃度較高之區域，藉此可緩和界面部分之鄰接之第1配線M1W間之電場。 圖22係顯示圖19之A-A部分之飛行時間二次離子質譜儀(TOF-SIMS)之CN-強度(氮濃度)分佈之圖表。即，圖20所說明之例之變化例。於形成於第1次絕緣性障壁層BR11上之第2次絕緣性障壁層BR12內，存在具有氮濃度峰值之區域，氮濃度之峰值較理想為於距第1絕緣性障壁膜BR1之下表面5~40 nm之範圍內具有氮濃度之峰值之構造。關於第2絕緣性障壁膜BR2亦具有相同之構造、相同之效果。因於1個膜中具有氮濃度峰值時，相較於界面具有峰值之情形破壞耐性更強，故而該構造較為理想。 以上，對由本發明者完成之發明基於其實施形態具體說明，當然本發明並非限定於上述實施形態，可於不脫離其主旨之範圍內進行各種變更，及可組合適當之實施形態。例如，可於實施形態1~3組合實施形態4。 另，於本申請案中亦包含下述發明。 一種半導體裝置之製造方法，其具有如下步驟： (a)準備半導體基板； (b)於上述半導體基板上，形成具有第1主表面，且具有特定之膜厚之層間絕緣膜； (c)於上述層間絕緣膜之上述第1主表面形成第1配線槽及第2配線槽； (d)於上述第1配線槽及第2配線槽內選擇性設置銅膜，形成第1配線及第2配線； (e)對上述第1配線、上述第2配線及上述層間絕緣膜之上述第1主表面實施含有氨之電漿處理；且 於上述步驟(e)中，於上述層間絕緣膜之上述第1主表面形成損傷層，且於上述損傷層之下方形成電場緩和層； 上述損傷層及上述電場緩和層之氮濃度較上述層間絕緣膜之氮濃度要大，上述電場緩和層之氮濃度較上述損傷層之氮濃度要大。
BARC‧‧‧防反射膜
BR1‧‧‧第1絕緣性障壁膜
BR2‧‧‧第2絕緣性障壁膜
BR11‧‧‧第1次絕緣性障壁膜
BR12‧‧‧第2次絕緣性障壁膜
BR21‧‧‧第1次絕緣性障壁膜
BR22‧‧‧第2次絕緣性障壁膜
CBR1‧‧‧第1導電性障壁膜
CBR2‧‧‧第2導電性障壁膜
CU1‧‧‧第1銅膜
CU2‧‧‧第2銅膜
DM1‧‧‧第1損傷層
DM2‧‧‧第2損傷層
ER1‧‧‧第1電場緩和層
ER2‧‧‧第2電場緩和層
EST1‧‧‧第1蝕刻阻止膜
EST2‧‧‧第2蝕刻阻止膜
INS1‧‧‧第1層間絕緣膜
INS2‧‧‧第2層間絕緣膜
INS3‧‧‧第3層間絕緣膜
INS21‧‧‧第1絕緣膜
INS31‧‧‧第2絕緣膜
INS32‧‧‧第3絕緣膜
M1V‧‧‧第1插塞電極
M2V‧‧‧第2插塞電極
M1W‧‧‧第1配線
M2W‧‧‧第2配線
NCH‧‧‧通道形成區域
NG‧‧‧閘極電極
NGI‧‧‧閘極絕緣膜
NSD‧‧‧源極區域或汲極區域
NW‧‧‧N型井區域
PCH‧‧‧通道形成區域
PG‧‧‧閘極電極
PGI‧‧‧閘極絕緣膜
PR1‧‧‧第1抗蝕劑膜
PR2‧‧‧第2抗蝕劑膜
PR3‧‧‧第3抗蝕劑膜
PR4‧‧‧第4抗蝕劑膜
PSD‧‧‧源極區域或汲極區域
PW‧‧‧P型井區域
Qn‧‧‧N型MISFET
Qp‧‧‧P型MISFET
SIL‧‧‧矽化物膜
ST‧‧‧元件分離膜
SUB‧‧‧P型半導體基板
VG1‧‧‧第1接觸孔
VG2‧‧‧第2接觸孔
WG1‧‧‧第1配線槽
WG2‧‧‧第2配線槽
圖1係一實施形態之半導體裝置之主要部分剖面圖。 圖2係一實施形態之半導體裝置之製造步驟中之主要部分剖面圖。 圖3係緊接圖2之半導體裝置之製造步驟中之主要部分剖面圖。 圖4係緊接圖3之半導體裝置之製造步驟中之主要部分剖面圖。 圖5係緊接圖4之半導體裝置之製造步驟中之主要部分剖面圖。 圖6係緊接圖5之半導體裝置之製造步驟中之主要部分剖面圖。 圖7係一實施形態之半導體裝置之層間絕緣膜之CN-強度分佈圖。 圖8係緊接圖6之半導體裝置之製造步驟中之主要部分剖面圖。 圖9係緊接圖8之半導體裝置之製造步驟中之主要部分剖面圖。 圖10係緊接圖9之半導體裝置之製造步驟中之主要部分剖面圖。 圖11係緊接圖10之半導體裝置之製造步驟中之主要部分剖面圖。 圖12係緊接圖11之半導體裝置之製造步驟中之主要部分剖面圖。 圖13係緊接圖12之半導體裝置之製造步驟中之主要部分剖面圖。 圖14係顯示一實施形態之半導體裝置之層間絕緣膜之CN-強度比與TDDB壽命之關係之圖表。 圖15係第2實施形態之半導體裝置之製造方法之氣體流量圖。 圖16係第2實施形態之層間絕緣膜之CN-強度分佈圖。 圖17係第2實施形態之半導體裝置之製造方法之氣體流量之變化例。 圖18係第3實施形態之層間絕緣膜之CN-強度分佈圖。 圖19係第4實施形態之半導體裝置之主要部分剖面圖。 圖20係第4實施形態之絕緣性障壁膜之CN-強度分佈圖。 圖21係第4實施形態之半導體裝置之製造方法之氣體流量圖。 圖22係第4實施形態之絕緣性障壁膜之CN-強度分佈圖之變化例。

Claims (9)

  1. 一種半導體裝置，其包含： 半導體基板； 層間絕緣膜，其形成於上述半導體基板之主表面上； 第1配線及第2配線，其等埋入於上述層間絕緣膜內，且彼此相鄰；及 絕緣性障壁膜(barrier film)，其係與上述第1配線、上述第2配線及上述層間絕緣膜接觸，且覆蓋上述第1配線、上述第2配線及上述層間絕緣膜；且 上述第1配線及上述第2配線主要包含銅膜； 上述層間絕緣膜在與上述絕緣性障壁膜相接之上述層間絕緣膜之表面部分包含含有氮之表面層； 上述表面層之氮濃度係具有如下之分佈：於與上述半導體基板之上述主表面垂直之第1方向，相較於靠近上述絕緣性障壁膜之區域，靠近上述半導體基板之上述主表面之區域變高； 上述第1配線之側面係：於上述第1方向，以從上述第1配線之上表面向上述第1配線之底面而上述第1配線之寬度縮小之方式傾斜； 上述第2配線之側面係：於上述第1方向，以從上述第2配線之上表面向上述第2配線之底面而上述第2配線之寬度縮小之方式傾斜。
  2. 如請求項1之半導體裝置，其中上述層間絕緣膜包含介電常數為3.0以下之絕緣膜。
  3. 如請求項2之半導體裝置，其中上述層間絕緣膜包含：矽(Si)、氧(O)、碳(C)。
  4. 如請求項3之半導體裝置，其中上述層間絕緣膜包含SiCOH膜。
  5. 如請求項1之半導體裝置，其中 上述表面層包含： 損傷層，其藉由電漿而形成於上述層間絕緣膜之表面部分； 電場緩和層，其藉由上述電漿而形成於上述損傷層之下部。
  6. 如請求項5之半導體裝置，其中上述損傷層係存在於自上述層間絕緣膜之上述主表面深4 nm之範圍。
  7. 如請求項5之半導體裝置，其中上述電場緩和層包含氮濃度之峰值區域。
  8. 如請求項7之半導體裝置，其中上述氮濃度之峰值區域係位於自上述層間絕緣膜之上述主表面5~20 nm之範圍。
  9. 如請求項5之半導體裝置，其中上述電場緩和層係以上述層間絕緣膜之上述主表面為基準，設置於較上述第1配線之厚度之1/2淺之位置。
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