EP1576664A1 - Method of forming a cap layer having anti-reflective characteristics on top of a low-k dielectric - Google Patents
Method of forming a cap layer having anti-reflective characteristics on top of a low-k dielectricInfo
- Publication number
- EP1576664A1 EP1576664A1 EP03781760A EP03781760A EP1576664A1 EP 1576664 A1 EP1576664 A1 EP 1576664A1 EP 03781760 A EP03781760 A EP 03781760A EP 03781760 A EP03781760 A EP 03781760A EP 1576664 A1 EP1576664 A1 EP 1576664A1
- Authority
- EP
- European Patent Office
- Prior art keywords
- layer
- silicon
- low
- dielectric
- silicon dioxide
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Withdrawn
Links
- 238000000034 method Methods 0.000 title claims abstract description 89
- 230000003667 anti-reflective effect Effects 0.000 title abstract description 5
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims abstract description 58
- MWUXSHHQAYIFBG-UHFFFAOYSA-N Nitric oxide Chemical compound O=[N] MWUXSHHQAYIFBG-UHFFFAOYSA-N 0.000 claims abstract description 39
- 238000000151 deposition Methods 0.000 claims abstract description 35
- 239000003989 dielectric material Substances 0.000 claims abstract description 33
- 230000008021 deposition Effects 0.000 claims abstract description 29
- 235000012239 silicon dioxide Nutrition 0.000 claims abstract description 29
- 239000000377 silicon dioxide Substances 0.000 claims abstract description 29
- 230000003287 optical effect Effects 0.000 claims abstract description 16
- BLRPTPMANUNPDV-UHFFFAOYSA-N Silane Chemical compound [SiH4] BLRPTPMANUNPDV-UHFFFAOYSA-N 0.000 claims abstract description 13
- 229910000077 silane Inorganic materials 0.000 claims abstract description 13
- 239000000126 substance Substances 0.000 claims abstract description 6
- 229910052751 metal Inorganic materials 0.000 claims description 35
- 239000002184 metal Substances 0.000 claims description 35
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 24
- 239000010703 silicon Substances 0.000 claims description 24
- 229910052710 silicon Inorganic materials 0.000 claims description 24
- 230000015572 biosynthetic process Effects 0.000 claims description 18
- IJGRMHOSHXDMSA-UHFFFAOYSA-N Atomic nitrogen Chemical compound N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 claims description 16
- 229910052757 nitrogen Inorganic materials 0.000 claims description 8
- 238000000059 patterning Methods 0.000 claims description 8
- 238000005498 polishing Methods 0.000 claims description 5
- 238000007517 polishing process Methods 0.000 abstract 1
- 239000010410 layer Substances 0.000 description 195
- 230000008569 process Effects 0.000 description 42
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 29
- 229910052802 copper Inorganic materials 0.000 description 29
- 239000010949 copper Substances 0.000 description 29
- 239000000758 substrate Substances 0.000 description 21
- 239000000463 material Substances 0.000 description 18
- 239000006117 anti-reflective coating Substances 0.000 description 17
- 229920002120 photoresistant polymer Polymers 0.000 description 16
- 230000004888 barrier function Effects 0.000 description 13
- 238000001465 metallisation Methods 0.000 description 11
- 239000004065 semiconductor Substances 0.000 description 10
- 239000007789 gas Substances 0.000 description 7
- 238000000623 plasma-assisted chemical vapour deposition Methods 0.000 description 7
- 239000002243 precursor Substances 0.000 description 6
- 229910052715 tantalum Inorganic materials 0.000 description 5
- GUVRBAGPIYLISA-UHFFFAOYSA-N tantalum atom Chemical compound [Ta] GUVRBAGPIYLISA-UHFFFAOYSA-N 0.000 description 5
- 229910052581 Si3N4 Inorganic materials 0.000 description 4
- 229910052782 aluminium Inorganic materials 0.000 description 4
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 4
- 230000008033 biological extinction Effects 0.000 description 4
- 238000000206 photolithography Methods 0.000 description 4
- HBMJWWWQQXIZIP-UHFFFAOYSA-N silicon carbide Chemical compound [Si+]#[C-] HBMJWWWQQXIZIP-UHFFFAOYSA-N 0.000 description 4
- 229910010271 silicon carbide Inorganic materials 0.000 description 4
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 4
- MZLGASXMSKOWSE-UHFFFAOYSA-N tantalum nitride Chemical compound [Ta]#N MZLGASXMSKOWSE-UHFFFAOYSA-N 0.000 description 4
- UFHFLCQGNIYNRP-UHFFFAOYSA-N Hydrogen Chemical compound [H][H] UFHFLCQGNIYNRP-UHFFFAOYSA-N 0.000 description 3
- 238000011161 development Methods 0.000 description 3
- 239000001257 hydrogen Substances 0.000 description 3
- 229910052739 hydrogen Inorganic materials 0.000 description 3
- 230000003071 parasitic effect Effects 0.000 description 3
- QGZKDVFQNNGYKY-UHFFFAOYSA-N Ammonia Chemical compound N QGZKDVFQNNGYKY-UHFFFAOYSA-N 0.000 description 2
- 230000008901 benefit Effects 0.000 description 2
- 239000006227 byproduct Substances 0.000 description 2
- 239000012159 carrier gas Substances 0.000 description 2
- 238000005229 chemical vapour deposition Methods 0.000 description 2
- 238000005137 deposition process Methods 0.000 description 2
- 230000005284 excitation Effects 0.000 description 2
- 230000005669 field effect Effects 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 238000004544 sputter deposition Methods 0.000 description 2
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 description 2
- 229910052721 tungsten Inorganic materials 0.000 description 2
- 239000010937 tungsten Substances 0.000 description 2
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 description 1
- UMVBXBACMIOFDO-UHFFFAOYSA-N [N].[Si] Chemical compound [N].[Si] UMVBXBACMIOFDO-UHFFFAOYSA-N 0.000 description 1
- 230000003213 activating effect Effects 0.000 description 1
- 230000006978 adaptation Effects 0.000 description 1
- 229940024548 aluminum oxide Drugs 0.000 description 1
- 229910021529 ammonia Inorganic materials 0.000 description 1
- 238000004140 cleaning Methods 0.000 description 1
- 238000010276 construction Methods 0.000 description 1
- 230000003247 decreasing effect Effects 0.000 description 1
- 230000002939 deleterious effect Effects 0.000 description 1
- 238000013461 design Methods 0.000 description 1
- 230000009977 dual effect Effects 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000004070 electrodeposition Methods 0.000 description 1
- 238000007772 electroless plating Methods 0.000 description 1
- 238000009713 electroplating Methods 0.000 description 1
- 230000003628 erosive effect Effects 0.000 description 1
- 230000001747 exhibiting effect Effects 0.000 description 1
- -1 for example Substances 0.000 description 1
- 238000012625 in-situ measurement Methods 0.000 description 1
- 238000011065 in-situ storage Methods 0.000 description 1
- 239000011810 insulating material Substances 0.000 description 1
- 230000003993 interaction Effects 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 238000005259 measurement Methods 0.000 description 1
- 125000004433 nitrogen atom Chemical group N* 0.000 description 1
- 238000009832 plasma treatment Methods 0.000 description 1
- 238000007747 plating Methods 0.000 description 1
- 239000010421 standard material Substances 0.000 description 1
- 238000012360 testing method Methods 0.000 description 1
- 239000010936 titanium Substances 0.000 description 1
- 229910052719 titanium Inorganic materials 0.000 description 1
- 230000007704 transition Effects 0.000 description 1
- PQDJYEQOELDLCP-UHFFFAOYSA-N trimethylsilane Chemical compound C[SiH](C)C PQDJYEQOELDLCP-UHFFFAOYSA-N 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
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- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
- H01L21/02112—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
- H01L21/02123—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon
- H01L21/02164—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material being a silicon oxide, e.g. SiO2
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
- H01L21/02112—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
- H01L21/02123—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon
- H01L21/02126—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material containing Si, O, and at least one of H, N, C, F, or other non-metal elements, e.g. SiOC, SiOC:H or SiONC
- H01L21/0214—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material containing Si, O, and at least one of H, N, C, F, or other non-metal elements, e.g. SiOC, SiOC:H or SiONC the material being a silicon oxynitride, e.g. SiON or SiON:H
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- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
- H01L21/022—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates the layer being a laminate, i.e. composed of sublayers, e.g. stacks of alternating high-k metal oxides
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- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
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- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
- H01L21/02205—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates the layer being characterised by the precursor material for deposition
- H01L21/02208—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates the layer being characterised by the precursor material for deposition the precursor containing a compound comprising Si
- H01L21/02211—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates the layer being characterised by the precursor material for deposition the precursor containing a compound comprising Si the compound being a silane, e.g. disilane, methylsilane or chlorosilane
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- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
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- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02225—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
- H01L21/0226—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process
- H01L21/02263—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase
- H01L21/02271—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase deposition by decomposition or reaction of gaseous or vapour phase compounds, i.e. chemical vapour deposition
- H01L21/02274—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase deposition by decomposition or reaction of gaseous or vapour phase compounds, i.e. chemical vapour deposition in the presence of a plasma [PECVD]
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- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
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- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
- H01L21/76804—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics by forming tapered via holes
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- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76829—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers
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- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76829—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers
- H01L21/76832—Multiple layers
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- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/7684—Smoothing; Planarisation
Definitions
- the present invention relates to the formation of integrated circuits, and, more particularly, to the formation of metallization layers including a metal embedded into a dielectric material having a low permittivity to enhance device performance.
- metallization layers are formed by a dielectric layer stack including, for example, silicon dioxide and/or silicon nitride with aluminum as the typical metal. Since aluminum exhibits significant electromigration at higher current densities, it is being replaced by copper, which has a significantly lower electrical resistance, a higher thermal conductivity and a higher resistivity against electromigration. Although device characteristics may significantly improve by applying copper as the metallization metal, for devices having feature sizes of 0.13 ⁇ m and less, it turns out that, additionally, the well-established and well-known dielectric materials, silicon dioxide (k « 4.2) and silicon nitride (k > 5), have to be replaced by so-called low-k dielectric materials in order to effectively reduce signal propagation delay by interconnect lines. The transition from the well-known and well-established aluminum/silicon dioxide metallization layer to a low-k dielectric/copper metallization layer, however, is associated with a plurality of issues that must be dealt with.
- copper may not be deposited in higher amounts " in 1 an efficient manner by well- established deposition methods, such as chemical vapor deposition. Additionally, copper may not be efficiently patterned by anisotropic etch processes and therefore the so-called damascene technique is employed in forming metallization layers including copper.
- damascene technique the dielectric layer is deposited and then patterned with trenches and vias that are subsequently filled with copper' by plating methods, such as electroplating or electroless plating. In order to reliably fill the trenches and vias, a certain amount of "overfill" is required and necessitates the subsequent removal of the excess copper.
- CMP chemical mechanical polishing
- Typical barrier materials such as tantalum and tantalum nitride, exhibit a significantly higher hardness than the copper so that, at least at a last step of the CMP process, respective process parameters are selected to obtain a sufficiently high removal rate, thereby, however, jeopardizing the underlying soft low-k dielectric material. Since a certain degree of overpolish is required to reliably insulate the individual trenches and lines from each other, a significant polish of the low-k dielectric layer and also of the copper may occur, especially when the removal rate varies across the substrate surface.
- the final trenches and vias may then exhibit an undesired resistance variation due to fluctuations in their cross- sectional areas, thereby requiring that the process margins be set correspondingly wider.
- a further issue of patterning the low-k dielectric layer concerns the photolithography technique, as especially the damascene technique requires the formation of precisely registered trenches and vias over a low-k dielectric material, possibly including highly reflective copper regions. Consequently, an anti-reflective coating
- ARC is usually formed over the low-k dielectric material to minimize the back-reflection of light into a photoresist layer formed on the ARC layer.
- a semiconductor structure 100 comprises a substrate 101 including a first dielectric layer 102 in which a plurality of narrow metal regions 103 and a wide metal region 104 are formed.
- the substrate 101 may include a plurality of circuit elements (not shown), some or all of which may be electrically connected to one or more of the metal regions 103 and 104.
- the metal region may be comprised of any appropriate material, such as aluminum, copper, tantalum, titanium, tungsten, and the like.
- the first dielectric layer 102 may be comprised of any appropriate insulating material and, in sophisticated integrated circuits, the first dielectric layer 102 may be comprised of a low-k dielectric material.
- An etch stop layer 105 is formed over the first dielectric layer 102 and the metal regions 103, 104, followed by a second dielectric layer 106 substantially comprised of a low-k dielectric material in which highly conductive interconnect lines and vias are to be formed.
- Appropriate low-k materials may include hydrogen-containing silicon oxycarbide (SiCOH), or other silicon-containing materials, such as SiLK. Other appropriate low-K materials are MSQ, HSQ and the like.
- An anti-reflective coating layer 107 is located above the second dielectric layer
- the resist mask 108 comprises openings 109 and 110, the dimensions of which substantially correspond to the dimensions of the lines and vias to be formed in the second dielectric layer 106.
- a typical process for forming the semiconductor structure 100 as shown in Figure la may comprise the following processes.
- the etch stop layer 105 is formed by, for example, chemical vapor deposition.
- the etch stop layer 105 is formed of a low-k material so as to not unduly compromise the overall characteristics of the finally obtained insulating layer.
- Appropriate materials are silicon carbide and nitrogen-doped silicon carbide.
- the etch stop layer 105 may be comprised of silicon nitride and other dielectric materials having a relatively high k.
- the second dielectric layer 106 is formed by advanced deposition methods or by spin-on techniques, depending on the type of low-k material used. Irrespective of the method for forming the second dielectric layer 106, in general the mechanical properties significantly differ from those of a conventional dielectric material such as silicon dioxide.
- the anti-reflective coating layer 107 may be comprised of silicon-rich oxynitride, the optical characteristics of which may be adjusted by controlling the amount of silicon incorporated into the layer 107 during the deposition, by providing a specified ratio of the precursor gases during the deposition of the layer 107 to achieve a specified refractive index and extinction coefficient. Additionally the thickness of the layer 107 is controlled to finally match the optical characteristics to the underlying material layers and to the photoresist used for forming the resist mask 108.
- a proper adaptation of the anti-reflective coating layer 107 is especially important during the formation of trenches and vias over the highly reflective metal regions 103, 104.
- a layer of photoresist is formed on the anti- reflective coating layer 107, wherein a thickness and a composition of the photoresist is selected in conformity with the wavelength used for exposing the photoresist and the underlying anti-reflective coating layer 107.
- the photoresist is then developed to form the resist mask 108 including the openings 109 and 110.
- Figure lb schematically shows the semiconductor structure 100 in an advanced manufacturing stage. Openings 113 and 114 are formed in the etch stop layer 105, the second dielectric layer 106, and the anti- reflective coating layer 107 over the metal regions 103 and 104, respectively.
- a barrier layer 111 for example comprising tantalum and/or tantalum nitride, is formed on the anti-reflective coating layer 107 and within the openings 113 and 114.
- copper 112 is filled in the openings 113 and 114, wherein excess copper is also provided outside the openings 113 and 114.
- an anisotropic etch process is carried out to form the openings 113, l H in the anti-reflective coating layer 107, the low-k dielectric layer 106, and the etch stop layer 105. Due to the very different characteristics of these layers, varying etch parameters may be selected to finally obtain the openings 113, 114. In particular, the etch stop layer 105 exhibits a significantly lower etch rate than the low-k dielectric layer 106 to reliably stop the etch process on and in the etch stop layer 105, which is then opened by a different etch process.
- the barrier layer 111 is deposited by advanced sputter deposition techniques, wherein, depending on the type of material of the layer 106 and the metal to be filled in the opening 113, 114, an appropriate composition of the barrier layer 111 is selected.
- a silicon-based layer 106 with copper as the fill metal a bi-layer of tantalum/tantalum nitride is frequently used as the barrier layer 111.
- a copper seed layer (not shown) is sputter deposited on the barrier layer 111 and then the bulk copper is deposited by electrochemical techniques.
- Figure lc schematically depicts the semiconductor structure 100 with a completed metallization layer 120 including the low-k dielectric layer 106 and the copper-filled trenches 113, 114.
- the excess copper of the layer 112, shown in Figure lb is removed by CMP, wherein typically a multi-step process is performed to effectively remove the excess copper and planarize the surface of the structure 100.
- the barrier layer 111 outside the trenches 113 and 114 is also removed in order to electrically insulate neighboring trenches from each other.
- the anti-reflective coating layer 107 typically exhibiting a relatively high k value, is removed so as to not unduly compromise the low-k characteristics of the metallization layer 120.
- a certain amount of the dielectric material of the layer 106 and of the copper in the trenches 113, 114 may also be removed, wherein the degree of overpolishing depends on the type of structure, its position on the substrate surface since the removal rate may vary across the substrate diameter, and the like.
- the removal rate at the relatively closely spaced trenches 113 may be higher than at the substrate location in the vicinity of the isolated trench 114. Due to the reduced mechanical stability of the low-k dielectric layer 106, a significant variation of the layer thickness may occur due to erosion, as indicated by 121, which finally results in a corresponding variation of the line resistance of the trenches 113.
- incompletely removing the anti-reflective coating layer 107 is not a promising option since the relatively high k value may result in substantial variations in the parasitic RC time constants in regions with minimally removed anti- reflective coating layer 107.
- the present invention is generally directed to a method of forming a cap layer that sufficiently protects the low-k dielectric layer during chemical mechanical polishing, and additionally allows the adjustment of the optical characteristics thereof within a single deposition chamber without unduly adding complexity to the deposition process.
- a method comprises the formation of a multi-layer stack over a dielectric layer comprised of a low-k dielectric material by forming a layer of silicon dioxide over the low-k dielectric layer. Furthermore, a silicon-rich oxynitride layer is formed during the formation of the layer of silicon dioxide to thereby adjust at least one optical characteristic of the multi-layer stack so as to reduce back reflection from the low-k dielectric layer.
- a method of forming a metal region in a low-k dielectric material comprises the deposition of a silicon dioxide based multi-layer in a plasma ambient over a layer including the low-k dielectric material.
- a recessed portion is formed by photolithography, wherein the multi-layer reduces back reflection.
- the recessed portion is then filled with a metal. Finally, excess metal and a portion of the multi-layer are removed by chemical mechanical polishing.
- Figures la-lc schematically show cross-sectional views of a semiconductor structure including a low-k dielectric layer that is patterned in accordance with a conventional process flow;
- Figures 2a-2c schematically show cross-sectional views during patterning of a dielectric layer including a low-k dielectric material in accordance with illustrative embodiments of the present invention
- Figure 3 schematically shows a deposition tool for plasma enhanced chemical vapor deposition
- PECVD PECVD
- a semiconductor structure 200 comprises a substrate 201 including a dielectric layer 202 comprised of a dielectric material, such as a standard material, for example, silicon dioxide, silicon nitride and the like, or a low-k dielectric material.
- the dielectric layer 202 may comprise a metal region 203 over which a trench or via is to be formed.
- the substrate As previously noted with reference to Figures la-lc, the substrate
- etch stop layer 205 is formed over the dielectric layer 202 and the metal region 203, wherein the etch stop layer 205 may be comprised of any appropriate material having a high etch selectivity with respect to an overlying dielectric layer 206 that is substantially comprised of a low-k dielectric material.
- Suitable materials for the dielectric layer 206 may include hydrogen-containing silicon oxycarbide (SiCOH), porous SiCOH, SiLK, porous SiLK, HSQ, MSQ, and the like.
- a multi-layer stack 230 is formed on the dielectric layer 206, wherein, in one embodiment, the multi-layer stack 230 comprises a first layer 231 substantially comprised of silicon dioxide, a second layer 232, substantially comprised of a silicon-rich oxynitride and a protection layer 233 having a significantly reduced amount of nitrogen atoms.
- the multi-layer stack 230 will also be referred to as a silicon dioxide based layer due to the silicon dioxide present in the multilayer stack and due to the formation sequence, as will be described below.
- the first, second and the protection layers 231, 232 and 233 of the multi-layer stack 230 have respective thicknesses 234, 235 and 236.
- the optical characteristics of the multi-layer stack 230 are determined by the respective thicknesses and the composition of the individual layers. In particular, the optical characteristics, such as index of refraction and extinction coefficient, of the second layer 232 may be adjusted by correspondingly selecting the amount of silicon and nitrogen contained therein.
- a photoresist mask 208 is formed on the multi-layer stack 230 with an opening 210 formed therein. The dimensions of the opening 210 substantially correspond to the dimensions of a trench or via to be formed in the low-k dielectric layer 206.
- the dielectric layer 202 and the metal region 203 may be formed in accordance with well-known and well-established process techniques, which depend on the type of metallization layer considered. If, for example, the dielectric layer 202 and the metal region 203 are to represent contact portions to underlying circuit elements, such as transistors, the formation sequence may include process steps such as depositing silicon dioxide and tungsten as a contact metal so as to obtain the layer 202 and the metal region 203.
- the etch stop layer 205 may be deposited, for example, by plasma enhanced chemical vapor deposition (PECVD) from appropriate precursor gases.
- PECVD plasma enhanced chemical vapor deposition
- FIG 3 schematically depicts a PECVD tool 300 in a simplified manner.
- the deposition tool 300 comprises a process chamber 301 including a plasma excitation means 302 that is connected to a power source 303, such as an RF generator.
- a source of precursor gases 304 is connected via a controllable valve assembly 305 with the process chamber 301.
- An outlet 306 is connected to suitable means (not shown) configured to remove gases and by-products from the process chamber 301 and to maintain a required pressure within the chamber 301.
- the deposition tool 300 comprises a substrate holder 307 configured to receive and hold a substrate, such as the substrate 201 shown in Figure 2a.
- the substrate holder 307 may comprise a controllable heater 308 for maintaining the temperature of the substrate 201 within a specified range.
- a plasma ambient is established within the process chamber 301 by activating the RF generator 303 and feeding appropriate precursor and carrier gases to the chamber 301.
- etch stop layer 205 is substantially comprised of silicon carbide and/or a nitrided silicon carbide layer, respective precursor gases, such as 3MS (trimethylsilane) and ammonia may be supplied.
- the low-k dielectric layer 206 is formed, for example by PECVD, from appropriate precursor gases, thereby using a deposition tool as shown in Figure 3.
- silicon-based low-k dielectric materials may be deposited from 3MS in accordance with well-known process recipes.
- the dielectric layer 206 may be formed by spin-on techniques to thereby form, for example, a layer of MSQ or
- the present invention is not limited to the type of low-k material and may be used with any type of low-k material, irrespective of the way the layer 206 is manufactured.
- the substrate 201 may be placed in a deposition tool, such as the tool 300, or may be maintained within the process chamber 301 when the low-k dielectric layer 206 has been deposited by PECVD.
- the first layer 231, substantially comprised of silicon dioxide, is formed from silane and nitrogen oxide (N 2 0).
- the pressure within the chamber 301 may be maintained in the range of approximately 2-4 Torr with a ratio of silane :nitrogen oxide in the range of approximately 1/45:1/55. Thereby, the flow rate of nitrogen oxide may be adjusted to approximately 3500-4500 seem and the flow rate of silane to approximately 60-100 seem.
- the RF power supplied to the plasma excitation means 302 may be maintained within a range of approximately 150-450
- the temperature of the substrate 201 is maintained within a range of approximately 350-450°C.
- a deposition rate of approximately 2.5-4 nm/second which will hereinafter also be referred to as low deposition rate process, may be obtained. Since the deposition rate is known in advance with sufficient accuracy, for example, by performing one or more test runs, the thickness 234 of the layer 231 may be controlled by adjusting the deposition time. In other embodiments, the thickness 234 may be controlled by an in situ measurement carried out with an appropriate measurement tool (not shown), such as an ellipsometer optically coupled to the process chamber 301.
- a higher deposition rate may be obtained by the following process parameters.
- the silane flow rate is adjusted to approximately 100-400 seem, the silane nitrogen oxide (N 2 0) ratio is in the range of approximately 1/10 to 1/20, whereas the remaining parameters may be adjusted to the values specified above in the low deposition rate process. With this parameter setting, a deposition rate of approximately 10-30 nm second is obtained.
- a pump step may be carried out so as to remove gas residuals and by-products of the preceding deposition process. Therefore, the pressure is adjusted to a range of approximately 4-8 Torr while supplying nitrogen as a carrier gas with a flow rate of approximately 7000-9000 seem. Furthermore, the silane/nitrogen oxide ratio is increased to approximately 2-3, wherein a typical flow rate for silane is in the range of 400-600 seem and that of nitrogen oxide is correspondingly adjusted. With an RF power in the range of approximately 300-600 Watts with the substrate temperature maintained in substantially the same range as in the preceding deposition step, a deposition rate of approximately 8-12 nm/second is achieved.
- the optical characteristics of the multi-layer stack 230 may be tuned by adjusting the respective thicknesses of the individual layers and especially by varying the silicon and nitrogen contents in the second layer 232.
- the refractive index of the second layer 232 may be adjusted to 2.20-2.60 and the extinction coefficient to approximately 0.80-0.90 for an exposure wavelength of 248 ran.
- the first layer 231 which is substantially comprised of silicon dioxide, exhibits relatively uniform optical characteristics with a refractive index in the range of approximately 1.40-1.47 at 673 nm with only slight variations.
- the anti-reflective characteristics of the multi-layer stack 230 may then be suitably adjusted by controlling the optical characteristics and/or the thickness of the second layer 232.
- the thickness 234 of the first layer 231 is adjusted within a range of approximately 20-120 nm, wherein the low deposition rate process may be used for a range of approximately 20-50 nm and the high deposition rate process may be used for the range of approximately 50-120 nm, whereas the thickness 235 of the second layer 232 is adjusted to a range of approximately 30-90 nm.
- the protection layer 233 is formed on the second layer 232 with a significantly reduced concentration of nitrogen, especially at a surface 237 thereof, which is in contact with a photoresist layer formed thereon.
- the protection layer 233 may be formed by a plasma treatment in a nitrogen oxide (N 2 0) ambient at a pressure of approximately 3.0-5.0 Torr at a temperature of approximately 350-450°C, using an RF power of approximately 50-200 Watts, wherein a flow rate of the nitrogen oxide (N 2 0) is set to approximately 250-600 seem.
- a thickness 236 of the protection layer 233 within a range of approximately 1-4 nm is obtained, wherein, especially at the surface 237, a majority of the silicon nitrogen bondings is replaced by a silicon oxygen bonding.
- the formation of the protection layer 233 may be carried out immediately after the deposition of the second layer 232.
- a layer of photoresist is deposited on the multi-layer stack 230, wherein a layer thickness of the photoresist, as well as the type and composition thereof, is selected in conformity with the photolithography requirements.
- the optical characteristics such as the index of refraction and the extinction coefficient, as well as the individual thicknesses 234, 235 and 236 of the multi-layer stack, are adapted to the photoresist used so as to obtain a minimum variation of critical dimensions.
- the photoresist layer is exposed and developed to form the opening 210, wherein, during exposure, a back reflection of light into regions of the photoresist adjacent to the opening 210 is minimized. In this way, resist residuals within the opening 210, also referred to as footing and scumming, may be reduced or even completely avoided.
- Figure 2b schematically shows the semiconductor structure 200 with an opening 213 formed in the multi-layer stack 230, the low-k dielectric layer 206 and the etch stop layer 205.
- a barrier layer 211 is formed over the multi-layer stack 230 and within the opening 213, and a metal layer 212, for example comprised of copper, is formed over the structure 200 so as to substantially completely fill the opening 213.
- the opening 213 may be formed by a sequence of anisotropic etch processes, similarly as described with reference to Figure lb, and the barrier layer 211, which may be comprised of two or more sub-layers, for example including a tantalum/tantalum nitride layer, is then deposited by sputter deposition. Thereafter, a thin seed layer (not shown) is sputter deposited and then the bulk metal is deposited by a well-known electrochemical deposition method.
- the excess metal of the layer 212 is removed by chemical mechanical polishing, wherein additionally the barrier layer 211 outside the opening 213 is also removed.
- the multi- layer stack 230 may also be partially removed, wherein the first layer 231, substantially comprised of silicon dioxide, reliably protects the underlying low-k dielectric material of reduced mechanical stability.
- the protection layer 233 and the second layer 232 are substantially completely removed. Consequently, the overall dielectric constant of the finally obtained intra-layer dielectric is substantially determined by the low-k dielectric layer 206 as the second layer 232, having a high amount of nitrogen incorporated into it and thus having a relatively high dielectric constant, is removed.
- first layer 231 may also be removed so as to further minimize the overall dielectric constant. Since the first layer 231 exhibits a relatively low removal rate during the copper CMP process, the underlying low-k dielectric material of the layer 206 is reliably protected, even if slight process variations during the CMP process occur. Consequently, undesired removal of the low-k dielectric material is substantially avoided, and therefore the variations in dimensions of the metal-filled openings 213, and thus the variations in resistivity thereof, are also significantly reduced.
- Figure 2c schematically shows the semiconductor structure 200 after completion of the above- described CMP process.
- a silicon dioxide layer of reduced thickness, indicated by 23 la, is still formed over the low-k dielectric layer 206 so that CMP-induced damage of the layer 206 is minimized.
- the thickness of the layer 231a may be reduced to 20 nm and less so as to obtain a required low total dielectric constant of the intra-layer dielectric.
- a single damascene process technique is described, wherein the present invention is also applicable to any process scheme of the damascene technique, such as dual damascene methods and the like.
- a multi-layer stack for patterning a low-k dielectric is provided, wherein the multi-layer stack may preferably be formed in situ by a relatively inexpensive plasma enhanced deposition method allowing a high rate of throughput, for example 80 substrates per hour or more may be processed, wherein the low-k dielectric material is effectively protected during the CMP process for removing excess metal, and, at the same time, an efficient anti-reflective effect is obtained, allowing the patterning of the low-k dielectric material substantially without creating "footing and scumming" effects.
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Abstract
Description
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Applications Claiming Priority (5)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
DE10260619 | 2002-12-23 | ||
DE10260619A DE10260619B4 (en) | 2002-12-23 | 2002-12-23 | Process for producing a cover layer with antireflective properties on a low-k dielectric |
US10/463,910 US7030044B2 (en) | 2002-12-23 | 2003-06-16 | Method of forming a cap layer having anti-reflective characteristics on top of a low-k dielectric |
US463910 | 2003-06-16 | ||
PCT/US2003/035272 WO2004061949A1 (en) | 2002-12-23 | 2003-11-06 | Method of forming a cap layer having anti-reflective characteristics on top of a low-k dielectric |
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EP1576664A1 true EP1576664A1 (en) | 2005-09-21 |
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EP03781760A Withdrawn EP1576664A1 (en) | 2002-12-23 | 2003-11-06 | Method of forming a cap layer having anti-reflective characteristics on top of a low-k dielectric |
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EP (1) | EP1576664A1 (en) |
JP (1) | JP2006525651A (en) |
KR (1) | KR101127240B1 (en) |
AU (1) | AU2003287518A1 (en) |
WO (1) | WO2004061949A1 (en) |
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JP2010171064A (en) * | 2009-01-20 | 2010-08-05 | Panasonic Corp | Semiconductor device and method of manufacturing same |
CN104919576B (en) | 2013-11-08 | 2020-09-04 | 瑞萨电子株式会社 | Semiconductor device and method for manufacturing the same |
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US6380096B2 (en) * | 1998-07-09 | 2002-04-30 | Applied Materials, Inc. | In-situ integrated oxide etch process particularly useful for copper dual damascene |
US6156640A (en) * | 1998-07-14 | 2000-12-05 | United Microelectronics Corp. | Damascene process with anti-reflection coating |
US6103456A (en) * | 1998-07-22 | 2000-08-15 | Siemens Aktiengesellschaft | Prevention of photoresist poisoning from dielectric antireflective coating in semiconductor fabrication |
US6294459B1 (en) * | 1998-09-03 | 2001-09-25 | Micron Technology, Inc. | Anti-reflective coatings and methods for forming and using same |
US6974766B1 (en) * | 1998-10-01 | 2005-12-13 | Applied Materials, Inc. | In situ deposition of a low κ dielectric layer, barrier layer, etch stop, and anti-reflective coating for damascene application |
US6255717B1 (en) * | 1998-11-25 | 2001-07-03 | Advanced Micro Devices, Inc. | Shallow trench isolation using antireflection layer |
US6291363B1 (en) * | 1999-03-01 | 2001-09-18 | Micron Technology, Inc. | Surface treatment of DARC films to reduce defects in subsequent cap layers |
JP3328230B2 (en) * | 1999-06-29 | 2002-09-24 | 山形日本電気株式会社 | Method of manufacturing antireflection film by plasma CVD |
US20020024139A1 (en) | 2000-02-04 | 2002-02-28 | Chan Simon S. | Combined capping layer and ARC for CU interconnects |
JP2002329779A (en) * | 2001-04-27 | 2002-11-15 | Mitsubishi Electric Corp | Semiconductor device and its fabrication method |
-
2003
- 2003-11-06 EP EP03781760A patent/EP1576664A1/en not_active Withdrawn
- 2003-11-06 AU AU2003287518A patent/AU2003287518A1/en not_active Abandoned
- 2003-11-06 KR KR1020057011804A patent/KR101127240B1/en not_active IP Right Cessation
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- 2003-11-06 JP JP2005508530A patent/JP2006525651A/en active Pending
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JP2006525651A (en) | 2006-11-09 |
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AU2003287518A1 (en) | 2004-07-29 |
KR20050093797A (en) | 2005-09-23 |
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