KR20050093797A - Method of forming a cap layer having anti-reflective characteristics on top of a low-k dielectric - Google Patents

Abstract

A method of forming a multi-layer stack (230) over a low-k dielectric layer (206) is disclosed, wherein the multi- layer stack (230) provides an improved anti-reflective effect and an enhanced protection of the underlying low-k dielectric material during the chemical mechanical polishing process. The multi-layer stack (230) comprises silicon dioxide based sub-layers (231, 232, 233), which may be formed in a highly efficient, non-expensive plasma enhanced deposition method, wherein the optical characteristics may be adjusted by varying a ratio of silane and nitrogen oxide during the deposition.

Description

METHODS OF FORMING A CAP LAYER HAVING ANTI-REFLECTIVE CHARACTERISTICS ON TOP OF A LOW-K DIELECTRIC

FIELD OF THE INVENTION The present invention generally relates to the formation of integrated circuits and, more particularly, to the formation of metallization layers comprising metal embedded in a dielectric material having a low-k dielectric constant to improve device performance. It is about.

In modern integrated circuits, minimum feature sizes, such as the channel length of a field effect transistor, reach a deep sub-micron range, so that the performance of these circuits in terms of speed and power consumption is reduced. Steadily increased. As the size of the individual circuit elements is significantly reduced, for example as the switching speed of the transistor elements is improved, the space available for the wiring lines electrically connecting the individual circuit elements is also reduced. As a result, in order to compensate for the reduction in the area available per chip and the increase in the number of circuit elements, the dimensions of these wiring lines must be reduced. In integrated circuits with minimum dimensions of approximately 0.35 μm, the limiting factor of device performance is the signal propagation delay caused by the switching speed of the transistor elements. However, as the channel length of the transistor elements now reaches 0.18 μm or less, the signal propagation delay is no longer determined by the field effect transistors, and has been found to be limited by the proximity of the wiring lines due to the increased package density of the circuits. This is because the capacitance between lines increases with the decrease in the conductivity of the lines due to the reduction in the cross-sectional area of the lines. Increased parasitic RC time constants due to increased line-to-line capacitance and high line resistance will not readily be compensated without the introduction of a new type of material to form metallization layers.

Generally, the metallization layers are formed by a dielectric layer stack, which includes, for example, silicon dioxide and / or silicon nitride together with aluminum as a common metal. Since aluminum exhibits very large electromigration at high current densities, aluminum is replaced by copper, which has significantly lower electrical resistance, higher thermal conductivity, and higher intrinsic resistance to electron transfer. Has resistance. Although device properties have been significantly improved by using copper as the metallization metal, for devices with feature sizes of 0.13 μm or less, additionally, the well-known and well-known dielectric materials, silicon dioxide (k ≒ 4.2) and silicon nitride (k> 5), has proven to be replaced by so-called low-k dielectric materials in order to effectively reduce the signal propagation delay caused by the wiring lines. The transition from the famous and well known aluminum / silicon dioxide metallization layers to low-k dielectric / copper metallization layers causes a number of problems that must be addressed.

For example, copper may not be deposited in large amounts in an efficient manner by well-established deposition methods such as chemical vapor deposition. In addition, copper cannot be efficiently etched by an anisotropic etch process, so the so-called damascene technique is used to form metallization layers comprising copper. Generally, in damascene technology, a dielectric layer is deposited and then patterned into trenches and vias, which are then electroplated or electroless plating. Copper is filled by plating methods such as). In order to reliably fill trenches and vias, a certain amount of “overfill” is required and subsequently removal of the excess copper is required. Although removing one or more materials from the substrate surface with a sufficiently high removal rate without excessively affecting the underlying material layer is a complex task, it removes excess copper and further flattens the surface of the metallization layer. Chemical mechanical polishing (CMP) has proven to be a practical process technique.

The situation is further complicated when low-k dielectric materials are provided in place of the famous silicon dioxide, since the properties of the low-k dielectric materials are generally quite different from those of silicon dioxide, especially in terms of mechanical stability. to be. Since copper readily diffuses in a plurality of dielectric materials, one or more barrier layers are typically provided prior to the deposition of the copper and such barrier layers are provided to provide electrically insulated wiring lines and vias. Must be removed with copper. Typical barrier materials such as tantalum and tantalum nitride exhibit significantly greater hardness than copper, so that each process parameter (at least in the last step of the CMP process) has a sufficiently large removal rate. Is selected, but the underlying soft low-k dielectric material is at stake. Because some degree of overpolish is required to reliably insulate each of the individual trenches and lines, a significant amount of low-k dielectric layer and also copper is polished, especially when the removal rate varies with the substrate surface. This is especially true. Then, since the final trenches and vias exhibit undesirable resistance variations due to variations in their cross-sectional area, the process margin needs to be set broadly correspondingly.

Another problem of patterning a low-k dielectric layer relates to the photolithography technique, in particular the damascene technique on top of the low-k dielectric material (possibly including highly reflective copper regions). This is because it requires the formation of trenches and vias with precision. As a result, an anti-reflective coating (ARC) is generally formed over the low-k dielectric material to minimize back-reflection of light into the photoresist layer formed on the ARC layer.

Referring now to FIGS. 1A-1C, a general prior art process for patterning low-k dielectric materials is now described. In FIG. 1A, a semiconductor substrate 100 includes a substrate 101, which includes a first dielectric layer 102 having a plurality of narrow metal regions 103 and a wide metal region 104 formed therein. ). The substrate 101 includes a plurality of circuit elements (not shown), some or all of the circuit elements being electrically connected to one or more of the metal regions 103 and 104. The metal region includes any suitable material such as aluminum, copper, tantalum, titanium, tungsten. The first dielectric layer 102 comprises any suitable insulating material, and in sophisticated integrated circuits the first dielectric layer 102 comprises a low-k dielectric material. An etch stop layer 105 is formed over the first dielectric layer 102 and the metal regions 103, 104, and then a second dielectric layer comprising substantially low-k dielectric material is formed. Very conductive wiring lines and vias are formed inside the second dielectric layer. Suitable low-k materials include hydrogen-containing silicon oxycarbide (SiCOH), or other silicon-containing materials such as SiLK. Other suitable low-k materials are such as MSQ, HSQ. An anti-reflective coating layer 107 is formed over the second dielectric layer 106, and a resist mask 108 is formed over the antireflective coating layer 107. The resist mask 108 includes openings 109 and 110, the dimensions of which substantially correspond to the dimensions of the lines and vias formed inside the second dielectric layer 106.

As shown in FIG. 1A, a general process of forming the semiconductor structure 100 includes the following processes. After the substrate 101 with the first dielectric layer 102 and the metal regions 103 and 104 formed therein is provided, the etch stop layer 105 is formed, for example by chemical vapor deposition, Here, the first dielectric layer 102 and the metal regions 103 and 104 include substantially the same steps as the process steps described below. Generally, the etch stop layer 105 is formed of low-k materials so as to not unduly impair the overall properties of the resulting insulating layer. Suitable materials are silicon carbide and nitrogen-doped silicon carbide. In less critical applications, the etch stop layer 105 includes silicon nitride and other dielectric materials having a relatively high-k. Thereafter, the second dielectric layer 106 is formed by advanced deposition methods or spin-on techniques, depending on the type of low-k material used. Regardless of how the second dielectric layer 106 is formed, the mechanical properties generally vary significantly from those of conventional dielectric materials such as silicon dioxide. After formation of the low-k dielectric layer 106, the anti-reflective coating layer 107 is formed, wherein the optical properties of the anti-reflective coating layer are at a predetermined wavelength during subsequent photolithography steps. Adjusted to minimize back reflections. For example, the anti-reflective coating layer 107 includes silicon-rich oxynitride, the optical properties of which are adjusted by controlling the amount of silicon incorporated into the layer 107 during deposition. Bar control of the amount of silicon is achieved by providing a specified percentage of precursor gas during deposition of the layer 107 to achieve a specified refractive index and extinction coefficient. In addition, the thickness of the layer 107 is controlled such that optical properties finally match the underlying material layers and the photoresist used to form the resist mask 108. Proper adaptation of the anti-reflective coating layer 107 is particularly important when forming trenches and vias over highly reflective metal regions 103 and 104. A photoresist layer is then formed over the antireflective coating layer 107, the thickness and composition of the photoresist being selected according to the wavelength used to expose the photoresist and the underlying antireflective coating layer 107. After exposure, the photoresist is then developed to form a resist mask 108 comprising the openings 109, 110.

1B then shows the semiconductor structure 100 at a fabrication stage. Openings 113 and 114 are formed in the etch stop layer 105, the second dielectric layer 106, and the anti-reflective coating layer 107 over each of the metal regions 103 and 104. A barrier layer 111, for example tantalum and / or tantalum nitride, is formed over the antireflective coating layer 107 and inside the openings 113, 114. In addition, copper 112 is filled in the openings 113 and 114, where excess copper is also provided outside the openings 113 and 114.

Beginning with the configuration of FIG. 1A, an anisotropic etching process is performed to form openings 113, 114 in the antireflective coating layer 107, low-k dielectric layer 106, and etch stop layer 105. Because of the very different properties of the layers, different etching parameters are selected to finally obtain the openings 113 and 114. In particular, the etch stop layer 105 exhibits significantly lower etch rates than the low-k dielectric layer 106 in order to reliably stop the etch process on and within the etch stop layer 105. Is opened by. For example, after performing one or more cleaning steps to clean the exposed metal surfaces of the regions 103 and 104, the barrier layer 111 is subjected to an advanced sputter deposition technique. The appropriate composition of the barrier layer 111 is selected depending upon the material of the layer 106 and the type of metal to be filled in the openings 113 and 114. In the silicon-based layer 106 with copper as the filling metal, a bi-layer of tantalum / tantalum nitride is often used as the barrier layer 111. Thereafter, when copper is used as the metal, a copper seed layer is sputter deposited onto the barrier layer 111 and then bulk copper is deposited by electrochemical techniques.

1C shows the semiconductor structure 100 with a finished metallization layer 120 including a low-k dielectric layer 106 and the copper filled trenches 113, 114. As already mentioned, excess copper in the layer 112 shown in FIG. 1B is removed by CMP, where the excess copper is efficiently removed and the surface of the structure 100 is flattened. In general, a plurality of process steps are performed. During removal of excess copper, the barrier layer 111 outside of the trenches 113 and 114 is also removed to electrically insulate adjacent trenches from each other. In addition, the anti-reflective coating layer 107, which exhibits a relatively high-k value, is removed in order not to excessively compromise the low-k properties of the metallization layer 120. During removal of the barrier layer 111 and the anti-reflective coating layer 107, the dielectric material of the layer 106 and a certain amount of copper in the trenches 113, 114 are also removed, the degree of overpolishing of the structure Depending on the type and location on the substrate surface, the removal rate will vary according to the same as the substrate diameter. In FIG. 1C, the removal rate relative to the trenches 113 is relatively higher than at adjacent substrate locations of the isolation trench 114. Since the mechanical stability of the low-k dielectric layer 106 has been reduced, significant variations in the layer thickness due to erosion 121 will occur, which ultimately accounts for the corresponding deviation in the line resistance of the trenches 113. Cause. As already mentioned, incomplete removal of the antireflective coating layer 107 is necessary because the relative high-k value causes substantial variation in the parasitic RC time constant in areas where the antireflective coating layer 107 has been minimally removed. Not a desirable option.

Accordingly, it has been proposed to provide a specific cap layer that protects the underlying low-k dielectric layer during the CMP process prior to the formation of the antireflective coating layer 107. However, the formation of additional cap layers and antireflective coating layers adds additional complexity and cost.

Thus, in view of the problems defined above, there is a need for an improved technique for patterning a low-k dielectric material layer.

BRIEF DESCRIPTION OF THE DRAWINGS The present invention may be understood with reference to the following description in conjunction with the accompanying drawings, wherein like reference numerals refer to like elements, and the drawings are as follows:

1A-1C show cross sections of a semiconductor structure including a low-k dielectric layer patterned according to a conventional process flow;

2A-2C illustrate cross sections during patterning of a dielectric layer comprising a low-k dielectric material in accordance with exemplary embodiments of the present invention; And

3 illustrates a deposition tool for plasma chemical vapor deposition (PECVD) suitable for forming a multi-cap layer as shown in FIGS. 2A-2C.

While the invention is susceptible to various modifications and alternative shapes, specific embodiments thereof are shown by way of example in the drawings and will be described in detail herein. The drawings and detailed description, however, are not intended to limit the invention to the particular forms disclosed, but to include all modifications, equivalents, and alternatives falling within the spirit and scope of the invention as defined by the appended claims. It is intended.

FIELD OF THE INVENTION The present invention generally relates to a method of forming a cap layer, which protects the low-k dielectric layer during chemical mechanical polishing, and further adds to a single deposition chamber without excessively increasing the complexity of the deposition process. ), Optical properties of the cap layer can be adjusted.

According to an exemplary embodiment of the invention, the method includes forming a multi-layer stack over a dielectric layer comprising a low-k dielectric material, which is a silicon dioxide layer over the low-k dielectric layer. It is made by forming. In addition, a silicon-rich oxynitride layer is formed during the formation of the silicon dioxide layer to reduce back reflection from the low-k dielectric layer by adjusting at least one optical property of the multi-layer stack.

In another exemplary embodiment of the present invention, a method of forming a metal region in a low-k dielectric material includes depositing a silicon dioxide based multi-layer in a plasma atmosphere over a layer comprising the low-k dielectric material. A recessed portion is formed by photolithography, where the multi-layer reduces back reflections. The recess is then filled with metal. As a result, excess metal and part of the multi-layer are removed by chemical mechanical polishing.

Exemplary embodiments of the invention are described below. For clarity, this specification does not describe all the features of an actual implementation. In the deployment of all these practical embodiments, in order to achieve the deployment's specific goals, such as following system related and business related constraints, various implementation specific decisions must be made, which will vary from implementation to implementation. It should also be noted that this development effort is complex and time consuming, but nevertheless is a routine task for those skilled in the art having the benefit of the present disclosure.

The present invention will now be described with reference to the accompanying drawings. Although the various structures and regions of the semiconductor device are shown in the figures as having very accurate and distinct configurations and profiles, those skilled in the art will recognize that such regions and structures may not be as accurate as shown in the figures. will be. In addition, the relative size of the various features and regions shown in the figures may be exaggerated or reduced compared to the size of these features or regions on the devices being manufactured. Nevertheless, the attached drawings are included to describe and explain illustrative examples of the present invention. The words and phrases used herein are to be understood and interpreted to have a meaning consistent with the understanding of those words and phrases by those skilled in the relevant art. The use of consistent terms or phrases herein is not intended to be construed as to include particular definitions of such terms or phrases, that is, any special definitions that differ from the ordinary and ordinary meanings understood by those skilled in the art. To the extent that any term or phrase is intended to have a special meaning, ie, meanings other than those understood by those skilled in the art, such particular definitions are clearly set forth in the specification in a limiting manner that directly and explicitly provides a particular definition for the term or phrase. Will be.

2A-2C and 3, exemplary embodiments of the present invention will be described. In FIG. 2A, semiconductor structure 200 includes a substrate 201, which includes, for example, a dielectric material, such as a standard material such as silicon dioxide, silicon nitride, or a low-k dielectric material. The dielectric layer 202 includes a metal region 203 on which trenches or vias are to be formed. As already mentioned with reference to FIGS. 1A-1C, the substrate 201 includes a plurality of circuit elements, one or more of which are electrically connected to the metal region 203. An etch stop layer 205 is formed over the dielectric layer 202 and the metal region 203, where the etch stop layer 205 overlies the dielectric layer 206 substantially comprising a low-k dielectric material. Any suitable material having a high etch selectivity relative to it. Suitable materials for the dielectric layer 206 include hydrogen-containing silicon oxycarbide (SiCOH), porous SiCOH, SiLK, porous SiLK, HSQ, MSQ. A multi-layer stack 230 is formed over the dielectric layer 206, and in one embodiment, the multi-layer stack 230 is substantially the first layer 231, silicon-rich oxynitite, including silicon dioxide. A second layer 232 substantially included in the ride, and a protection layer 233 having a significantly reduced amount of nitrogen atoms. The multi-layer stack 230 is also referred to as a silicon dioxide based layer because of the silicon dioxide present in the multi-layer stack and the formation sequence described below.

Each of the first, second, and protective layers 231, 232, and 233 of the multi-layer stack 230 has thicknesses 234, 235, and 236. The optical properties of the multi-layer stack 230 are determined by the thickness and composition of each of the individual layers. In particular, optical properties such as refractive index and extinction coefficient of the second layer 232 can be adjusted by correspondingly selecting the amounts of silicon and nitrogen contained therein. A photoresist mask 208 having an opening 210 therein is formed over the multi-layer stack 230. The dimensions of the opening 210 substantially correspond to the dimensions of the trench or via to be formed in the low-k dielectric layer 206.

Referring now to FIG. 2A as well as to FIG. 3, a process flow for forming the semiconductor structure 200 in accordance with example embodiments will now be described. The dielectric layer 202 and the metal region 203 are formed according to well-known and well known process technologies-depending on the type of metallization layer under consideration. For example, if the dielectric layer 202 and the metal region 203 represent contact portions for underlying circuit elements, such as transistors, the formation sequence may cause the layer 202 and the metal region 203 to become in contact with each other. Process steps such as depositing tungsten as contact metal and silicon dioxide to obtain. If the dielectric layer 202 should represent a low-k dielectric layer, the corresponding process steps may be similar to the processes described below when referring to the step of forming and patterning the dielectric layer 206. Will include them. The etch stop layer 205 is then deposited by, for example, plasma chemical vapor deposition (PECVD) from suitable precursor gases.

3 shows a PECVD tool 300 in a simplified manner. The deposition tool 300 includes a process chamber 301 having plasma excitation means 302 connected to a power source such as an RF generator. A source 304 of precursor gas is connected to the process chamber 301 through a controllable valve assembly 305. An outlet 306 is connected to suitable means (not shown) configured to remove gases and by-products from the process chamber 301 and to maintain the required pressure inside the chamber 301. In addition, the deposition tool 300 includes a substrate holder 307 configured to receive and hold the substrate 201 shown in FIG. 2A. The substrate holder 307 includes a controllable heater 308 to maintain the temperature of the substrate 201 in a specific range.

After installing the substrate 201 on the substrate holder 307, the plasma atmosphere is activated by activating the RF generator 303 and injecting bulb and carrier gases into the chamber 301. ) Is formed inside. If the etch stop layer 205 comprises substantially silicon carbide and / or nitrided silicon carbide layers, respective precursor gases such as 3MS (edisilane trimersilane) and ammonia will be supplied.

The low-k dielectric layer 206 is then formed from suitable precursor gases, such as by PECVD, using a deposition tool as shown in FIG. 3. For example, silicon-based low-k dielectric materials are deposited from 3MS according to well known process methods. In other embodiments, the dielectric layer 206 is formed by spin-on techniques to form an MSQ or HSQ (hydrogen cisquioxane) layer, for example. It is to be appreciated that the present invention is not limited to the low-k material type and can be used for all low-k material types, regardless of how the layer 206 is manufactured. The substrate 201 is then placed in a deposition tool, such as the tool 300, or maintained in the process chamber 301 when the low-k dielectric layer 206 is deposited by PECVD. In a particular embodiment, the first layer 231 comprising substantially silicon dioxide is formed from silane and nitrogen oxide (N ₂ O). During the deposition of the silicon dioxide, the pressure inside the chamber 301 is maintained in the range of approximately 2-4 torr with a silane: nitrogen oxide ratio in the range of approximately 1/45: 1/55. Thus, the flow rate of the nitrogen oxide can be adjusted to approximately 3500-4500 sccm and the flow rate of silane can be adjusted to approximately 60-100 sccm. The RF power supplied to the plasma excitation means 302 is maintained in the range of approximately 150-450 Watts, where the temperature of the substrate 201 is maintained in the range of approximately 350-450 ° C. With the parameter range specified above, a deposition rate of approximately 2.5-4 nm / sec, also referred to as a low deposition rate process below, is obtained. Since the deposition rate is already sufficiently accurate, for example through one or more test runs, the thickness 234 of the layer 231 can be controlled by adjusting the deposition time. In other embodiments, the thickness 234 is controlled by an in situ measurement performed with a suitable measuring tool (not shown), the measuring tool being optically coupled to the process chamber 301. It's like a connected ellipsometer.

In another exemplary embodiment, a high deposition rate, called a high deposition rate process, is obtained by the following process parameters. The silane flow rate is adjusted approximately 100-400 sccm and the silane nitrogen oxide (N ₂ O) ratio is in the range of approximately 1/10 to 1/20, with the remaining parameters being specified for the low deposition rate process. The adjusted values are adjusted. In this parameter setting, the deposition rate is obtained at approximately 10-30 nm / second.

Prior to formation of the second layer 232, a pump step is performed to remove residual gases and byproducts of the previous deposition process. Therefore, while supplying nitrogen with a carrier gas having a flow rate of approximately 7000-9000 sccm, the pressure is adjusted in the range of approximately 4-8 Torr. In addition, the silane / nitrogen oxide ratio increases to approximately 2-3, where the general flow rate for silane is in the range of 400-600 sccm, and the flow rate of nitrogen oxide is adjusted accordingly. Deposition rates of approximately 8-12 nm / sec are achieved by maintaining RF power in the range of approximately 300-600 Watts and substrate temperature substantially the same as in the foregoing deposition step. As already mentioned, the optical properties of the multi-layer stack 230 are adjusted by adjusting the thicknesses of the individual layers respectively and in particular by changing the amounts of silicon and nitrogen in the second layer 232. . In the above specified range of silane: nitrogen oxide (N ₂ O), for an exposure wavelength of 248 nm, the refractive index of the second layer 232 is adjusted to 2.20-2.60 and the extinction coefficient is approximately 0.80-0.90 Is adjusted. In contrast, the first layer 231 substantially comprising silicon dioxide exhibits relatively homogeneous optical properties with a refractive index in the range of approximately 1.40-1.47 with very small deviations at 673 nm. Thus, for the required thickness of the first layer 231 selected according to the requirements of the CMP process that is subsequently performed, the antireflective properties of the multi-layer stack 230 are then the optical of the second layer 232. It can be adjusted appropriately by controlling the properties and / or thickness. In some exemplary embodiments, the thickness 234 of the first layer 231 is adjusted to be in the range of approximately 20-120 nm, and the thickness 234 of the first layer 231 is in the range of approximately 20-120 nm. Adjusted within, the low deposition rate process is used for the approximately 20-50 nm range and the high deposition rate process is used for the range of approximately 50-120 nm, while the thickness of the second layer 232 ( 235) is adjusted to a range of approximately 30-90 nm.

In a particular embodiment, the protective layer 233 is formed over the second layer 232 where the nitrogen concentration is significantly reduced (especially at the surface 237 in contact with the photoresist layer formed over the protective layer). The reduced amount of nitrogen in the protective layer 233 (especially at the surface 237) can significantly reduce or substantially completely avoid interactions with the photoresist using nitrogen, otherwise the interaction A photoresist residual is formed after development of the photoresist.

The protective layer 233 is formed by plasma treatment in a nitrogen oxide (N ₂ O) atmosphere, using approximately 50-200 Watts of RF power, approximately 3.0-5.0 Torr at a temperature of approximately 350-450 ° C. Pressure, where the flow rate of nitrogen oxide (N ₂ O) is set to approximately 250-600 sccm. In the specified parameter setting, the thickness 236 of the protective layer 233 is obtained in the range of approximately 1-4 nm, in particular most of the silicon nitrogen bonds in the surface 237 are replaced with silicon oxygen bonds. After deposition of the second layer 232, formation of the protective layer 233 is performed immediately.

A photoresist layer is then deposited over the multi-layer stack 230, where the thickness and the type and composition of the photoresist layer as well as the photolithography requirements are selected. As already mentioned, the individual thicknesses 234, 235, 236 of the multi-layer stack as well as optical properties such as refractive index and extinction coefficient are adapted to the photoresist used to obtain the minimum deviation of critical dimensions. Thereafter, the photoresist layer is exposed and developed to form an opening 210, during which the back reflection of light into the photoresist area adjacent to the opening 210 is minimized. In this way, resist residues (also called footing and scumming) inside the opening 210 are reduced or completely avoided.

2B shows the semiconductor structure 200 having a multi-layer stack 230, a low-k dielectric layer 206 and an opening 213 formed in the etch stop layer 205. A barrier layer 211 is formed over the multi-layer stack 230 and in the opening 213, and a metal layer 212 including, for example, copper is formed over the structure 200 to substantially the opening 213. Fully fill

The opening 213 is formed by an anisotropic etching process sequence similar to that described with reference to FIG. 1B, and then the barrier layer 211 is deposited by sputter deposition, wherein the barrier layer is formed of two or more subs. Consists of layers, for example tantalum / tantalum nitride layers. Thereafter, a thin seed layer (not shown) is sputter deposited and then the bulk metal is deposited by a well known electrochemical deposition method.

Thereafter, excess metal in the layer 212 is removed by chemical mechanical polishing, where further the barrier layer 211 outside the opening 213 is also removed. During the CMP process, the multi-layer stack 230 is also partially removed, where the first layer 231 substantially comprising silicon dioxide reliably protects the lower low-k dielectric material with reduced mechanical stability. . In an exemplary embodiment, the protective layer 233 and the second layer 232 are substantially completely removed. As a result, the overall dielectric constant of the finally obtained intra-layer dielectric is substantially determined by the low-k dielectric layer 206, in which a large amount of nitrogen is incorporated to produce a relatively high dielectric. This is because the second layer 232 having a constant is removed. In addition, a portion of the first layer 231 is also removed to further minimize the overall dielectric constant. Since the first layer 231 exhibits a relatively low removal rate during the copper CMP process, the low-k dielectric material of the underlying layer 206 is reliably protected even if slight process variations occur during the CMP process. do. As a result, the undesirable removal of the low-k dielectric material is substantially avoided, so that the variation in the dimensions of the openings 213 filled with the metal, and therefore in the resistance thereof, is also significantly reduced.

2C shows the semiconductor structure 200 after completion of the CMP process described above. A reduced thickness silicon dioxide layer, denoted 231a, is still formed over the low-k dielectric layer 206, thereby minimizing damage to the layer 206 caused by CMP. In one embodiment, the thickness of the layer 231a is reduced to 20 nm or less, thereby obtaining the required overall low dielectric constant of the inner layer dielectric.

Although the single damascene process technique has been described in the above examples, it should be appreciated that the present invention is also applicable to all process methods of the damascene technique, such as the dual damascene process.

As a result, according to the present invention, a multi-layer stack for patterning a low-k dielectric is provided, wherein the multi-layer stack is preferably relatively capable of high throughput (e.g. processing more than 80 substrates per hour). Formed in situ by an inexpensive plasma deposition method, the low-k dielectric material is effectively protected during the CMP process of removing excess metal, while at the same time achieving an effective antireflection effect, And substantially patterning the low-k dielectric material without creating a "scumming" effect. Because of the effective protection of the low-k dielectric layer during the CMP process, damage to the material is considerably reduced, especially in areas with dense structures. Thus, the variation of the sheet resistance of the corresponding metal structures is also significantly reduced. By thinning the multi-layer stack during the CMP process, the effective value of the dielectric constant can be kept very low to substantially avoid the deleterious effects of parasitic RC time constants.

The specific embodiments disclosed above are merely exemplary, and the invention is different but may be modified or practiced in a manner apparently equivalent to one skilled in the art having learned the disclosure. For example, the process steps disclosed above may be performed in a different order. Moreover, no limitations are made to the details of the structure or design shown herein except as described in the claims below. Accordingly, it is apparent that the above detailed description may be changed or modified and such changes are within the spirit and scope of the present invention. Accordingly, the scope of protection is set forth in the claims below.

Claims (18)

Forming a multi-layer stack (230) over the dielectric layer (206) by forming a silicon dioxide layer (231) over the dielectric layer (206) comprising a low-k dielectric material; And Silicon-rich oxynitride layer 232 during the formation of the silicon dioxide layer to adjust at least one optical property of the multi-layer stack 230 to reduce back reflection from the low-k dielectric layer. Forming said method. The method of claim 1, The silicon dioxide layer (231) is deposited from silane. The method of claim 1, After the formation of the silicon dioxide layer 231, The silicon-rich oxynitride layer (232) is formed by changing the deposition atmosphere. The method of claim 1, Wherein the thickness of the silicon dioxide layer (231) formed over the dielectric layer (206) is in the range of approximately 20-120 nm. The method of claim 1, Wherein the thickness of the silicon-rich oxynitride layer (232) is in the range of approximately 30-90 nm. The method of claim 1, And the optical properties are adjusted by varying the amount of silicon in the silicon-rich oxynitride layer (232). The method of claim 6, Characterized in that the amount of silicon is altered by adjusting the silane / nitrogen oxide (N ₂ O) ratio in the deposition atmosphere. The method of claim 1, And forming a nitrogen-depleted protective layer (233) in the surface region of said silicon-rich oxynitride layer (232). The method of claim 8, The protective layer (233) is formed by exposure to a nitrogen oxide (N ₂ O) plasma atmosphere. The method of claim 9, And the nitrogen oxide (N ₂ O) plasma atmosphere is formed by stopping the silane supply used during deposition of the silicon-rich oxynitride layer (232). The method of claim 8, The thickness of the protective layer (233) is in the range of approximately 1-5 nm. The method of claim 1, And forming a resist mask (208) over said silicon-rich oxynitride layer (232). The method of claim 12, Patterning the dielectric layer (206) with the resist mask (208) to form recesses in the dielectric layer (206). A method of forming a metal region in a low-k dielectric material, Depositing a silicon dioxide based multi-layer (230) in a plasma atmosphere over the layer (206) comprising the low-k dielectric material (while controlling the optical properties of the silicon dioxide based multi-layer); Forming a recessed portion (213), wherein the multi-layer (230) reduces back reflection for a specified wavelength length; Filling the recess with metal (212); And Removing excess metal and a portion of the multi-layer by chemical mechanical polishing. The method of claim 14, And the silicon dioxide based multi-layer (230) is deposited at least in part from silane. The method of claim 14, A metal region in a low-k dielectric material, characterized in that a silicon-rich oxynitride layer 232 is formed in the multilayer 230 by changing the deposition atmosphere during formation of the silicon dioxide based multi-layer 230. How to form. The method of claim 14, Wherein the thickness of the silicon-rich oxynitride layer (232) is in the range of approximately 30-90 nm. The method of claim 16, Wherein the optical properties are adjusted by varying the amount of silicon in the silicon-rich oxynitride layer (232).