CN104919576A - 半导体器件及其制造方法 - Google Patents

半导体器件及其制造方法 Download PDF

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Publication number
CN104919576A
CN104919576A CN201380011034.4A CN201380011034A CN104919576A CN 104919576 A CN104919576 A CN 104919576A CN 201380011034 A CN201380011034 A CN 201380011034A CN 104919576 A CN104919576 A CN 104919576A
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Prior art keywords
distribution
interlayer dielectric
film
semiconductor device
layer
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CN201380011034.4A
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CN104919576B (zh
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宇佐美达矢
三浦幸男
土屋秀昭
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Renesas Electronics Corp
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Renesas Electronics Corp
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    • H01L21/02068—Cleaning during device manufacture during, before or after processing of conductive layers, e.g. polysilicon or amorphous silicon layers
    • H01L21/02074—Cleaning during device manufacture during, before or after processing of conductive layers, e.g. polysilicon or amorphous silicon layers the processing being a planarization of conductive layers
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Abstract

本发明提供一种半导体器件，其具有：层间绝缘膜(INS2)；在层间绝缘膜(INS2)内形成的相邻的Cu配线(M1W)；以及与层间绝缘膜(INS2)的表面和Cu配线(M1W)的表面接触、且将层间绝缘膜(INS2)和Cu配线(M1W)覆盖的绝缘性阻挡膜(BR1)。而且，在相邻的Cu配线(M1W)之间，层间绝缘膜(INS2)在其表面具有损伤层(DM1)，在比损伤层(DM1)深的位置具有电场缓和层(ER1)，该电场缓和层(ER1)具有比损伤层(DM1)的氮浓度高的氮浓度。

Description

半导体器件及其制造方法
技术领域
本发明涉及半导体器件及其制造方法，例如，能够适合利用于具备Cu配线的半导体器件以及其制造方法。
背景技术
在近年的半导体器件中，为了高速工作、低耗电等而必须适用Cu(铜)配线。Cu配线通过如下方法形成：在使用镶嵌(Damascene)法在半导体衬底上的层间绝缘膜上形成配线槽后，在该配线槽的内部以及层间绝缘膜上堆积Cu(铜)膜，接下来使用化学机械研磨(CMP：Chemical Mechanical Polishing)法在配线槽内选择性地留下Cu膜，由此形成Cu配线。对于层间绝缘膜，使用氧化硅膜等。
因为构成Cu配线的Cu与例如Al(铝)那样的配线材料相比，易于向氧化硅膜等层间绝缘膜中扩散，所以Cu配线的底面以及侧面由TiN(氮化钛)膜等导电性阻隔膜覆盖。另外，Cu配线的表面与相邻的层间绝缘膜的表面一同被绝缘性阻挡膜覆盖。
在这样的Cu配线构造中，由于Cu离子在层间绝缘膜与绝缘性阻挡膜的界面上的移动，产生Cu配线的TDDB(Time Dependence onDielectric Breakdown，经时击穿)。特别地在Cu-CMP后Cu表面被氧化而成为CuO时，Cu易于离子化从而TDDB劣化。为了使该Cu配线的TDDB特性提高，已知有如下技术：对Cu配线以及层间绝缘膜的表面实施氨(NH3)等离子体处理，将Cu配线表面的CuO还原为Cu，然后形成绝缘性阻挡膜。
另外，作为层间绝缘膜，为了降低配线间电容而研究了低介电常数的绝缘膜例如SiCOH等的使用。
在“Effective Cu Surface Pre-treatment for High-reliable22nm-node Cu Dual Damascene Interconnects with High Plasmaresistant Ultra Low-k Dielectric(k＝2.2)”(非专利文献1)中，公开了对形成于低介电常数的绝缘膜上的Cu配线实施氨等离子体处理的内容。另外，公开了如下内容：通过氨等离子体处理，在低介电常数的层间绝缘膜表面形成氧化膜那样的介电常数较高的损伤层(damage layer)，导致RC特性或可靠性下降。
现有技术文献
非专利文献
非专利文献1：F.Ito et al.，“Effective Cu Surface Pre-treatment forHigh-reliable 22nm-node Cu Dual Damascene Interconnects with HighPlasma resistant Ultra Low-k Dielectric(k＝2.2)”Advanced MetalizationConference October 5-7，2010
发明内容
本发明的发明人对使用低介电常数的绝缘膜作为层间绝缘膜的Cu配线进行研究，发现如下问题点。
半导体器件在不断精细化，Cu配线间空间变小，而电源电压仍大致恒定，存在对Cu配线间的层间绝缘膜施加的电场强度变大的倾向。另外，Cu配线依赖其制造方法而在膜厚方向上具有锥形状，在相邻的Cu配线的上端部之间施加的电场最高。也就是说，可以说层间绝缘膜与绝缘性阻挡膜的界面是最容易引起TDDB破坏(TDDB寿命下降)的部位。
进而，若通过CMP处理后的氨等离子体处理将低介电常数的层间绝缘膜的表面氧化以及氮化而形成损伤层，则由于损伤层部分的介电常数高于层间绝缘膜的介电常数，所以电场容易集中在损伤层部分，存在Cu配线间的TDDB寿命下降(恶化)的问题。
其他的课题和新的特征从本说明书的记述以及附图得以明确。
根据一实施方式，半导体器件具有：层间绝缘膜；在层间绝缘膜内形成的相邻的Cu配线；以及与层间绝缘膜的表面和Cu配线的表面接触、且将层间绝缘膜和Cu配线覆盖的绝缘性阻挡膜。而且，在相邻的Cu配线之间，层间绝缘膜在其表面具有损伤层，在比损伤层深的位置具有电场缓和层，该电场缓和层具有比损伤层的氮浓度高的氮浓度。
根据一实施方式，能够使具备Cu配线的半导体器件的TDDB寿命提高。
附图说明
图1是一实施方式的半导体器件的主要部分剖视图。
图2是一实施方式的半导体器件的制造工序中的主要部分剖视图。
图3是图2之后的半导体器件的制造工序中的主要部分剖视图。
图4是图3之后的半导体器件的制造工序中的主要部分剖视图。
图5是图4之后的半导体器件的制造工序中的主要部分剖视图。
图6是图5之后的半导体器件的制造工序中的主要部分剖视图。
图7是一实施方式的半导体器件的层间绝缘膜的CN－强度分布图。
图8是图6之后的半导体器件的制造工序中的主要部分剖视图。
图9是图8之后的半导体器件的制造工序中的主要部分剖视图。
图10是图9之后的半导体器件的制造工序中的主要部分剖视图。
图11是图10之后的半导体器件的制造工序中的主要部分剖视图。
图12是图11之后的半导体器件的制造工序中的主要部分剖视图。
图13是图12之后的半导体器件的制造工序中的主要部分剖视图。
图14是表示一实施方式的半导体器件的层间绝缘膜的CN－强度比与TDDB寿命的关系的图表。
图15是第二实施方式的半导体器件的制造方法的气体流动图。
图16是第二实施方式的层间绝缘膜的CN－强度分布图。
图17是第二实施方式的半导体器件的制造方法的气体流动图的变形例。
图18是第三实施方式的层间绝缘膜的CN－强度分布图。
图19是第四实施方式的半导体器件的主要部分剖视图。
图20是第四实施方式的绝缘性阻挡膜的CN－强度分布图。
图21是第四实施方式的半导体器件的制造方法的气体流动图。
图22是第四实施方式的绝缘性阻挡膜的CN－强度分布图的变形例。
具体实施方式
以下，基于附图对实施方式进行详细说明。此外，在用于说明实施方式的所有图中，对具有同一功能的部件标注同一附图标记，并省略重复的说明。另外，在以下的实施方式中，除特别需要时以外，原则上不重复同一或同样的部分的说明。
另外，在实施方式所使用的附图中，存在为了易于观察附图而即使是剖视图也省略剖面线的情况。另外，也存在为了易于观察附图而即使是俯视图也添加剖面线的情况。
(实施方式1)
图1是表示本实施方式的半导体器件的截面构造的主要部分剖视图。
在由硅形成的P型半导体衬底SUB的主面(表面)上，形成有多个P型阱区域PW和多个N型阱区域NW。在P型阱区域PW内形成有N型MISFET(Metal Insulator Semiconductor Field EffectTransistor，金属-绝缘体-半导体场效应晶体管)Qn(以下，记为N型MISFETQn)，在N型阱区域NW内形成有P型MISFET Qp(以下，记为P型MISFETQp)。在半导体衬底SUB的表面局部地形成有由氧化硅膜等绝缘膜构成的元件分离膜(元件分离区域)ST。元件分离膜ST在P型阱区域PW内以及N型阱区域NW内，规定N型MISFET形成区域以及P型MISFET形成区域。即，俯视观察时，在P型阱区域PW内的被元件分离膜ST包围的区域中形成一个或多个N型MISFET。另外，俯视观察时，在N型阱区域NW内的被元件分离膜ST包围的区域中形成一个或多个P型MISFETQp。N型MISFETQn包括：与元件分离膜ST相接的N型源极区域NSD以及N型漏极区域NSD；源极区域NSD与漏极区域NSD之间的沟道形成区域NCH；以及在沟道形成区域NCH上隔着栅极绝缘膜NGI形成的栅电极NG。在N型源极区域NSD、N型漏极区域NSD以及栅电极NG的表面上形成有硅化物膜SIL。P型MISFETQp包括：与元件分离膜ST相接的P型源极区域PSD以及P型漏极区域PSD；源极区域PSD与漏极区域PSD之间的沟道形成区域PCH；在沟道形成区域PCH上隔着栅极绝缘膜PGI形成的栅电极PG。在P型源极区域PSD、P型漏极区域PSD以及栅电极PG的表面上形成有硅化物膜SIL。
N型MISFETQn、P型MISFETQp以及元件分离膜ST被由氮化硅膜形成的作为绝缘膜的第一蚀刻阻挡膜EST1覆盖。并且，在第一蚀刻阻挡膜EST1上，形成有作为绝缘膜的第一层间绝缘膜INS1，第一层间绝缘膜INS1由BP(Boron，Phosphorus)-TEOS膜形成。在第一蚀刻阻挡膜EST1以及第一层间绝缘膜INS1上形成有多个第一接触孔VG1，在第一接触孔VG1内设置有金属导体膜即第一插塞式电极M1V。第一插塞式电极M1V与N型MISFETQn的源极区域NSD及漏极区域NSD、以及P型MISFETQp的源极区域PSD及漏极区域PSD电连接。第一插塞式电极M1V由氮化钛膜(TiN)和钨膜(W)的层叠构造构成。在第一层间绝缘膜INS1上形成第一接触孔VG1时，第一蚀刻阻挡膜EST1作为蚀刻阻挡层发挥功能。关于第一接触孔VG1形成时的蚀刻，在使第一层间绝缘膜INS1的蚀刻速率比第一蚀刻阻挡膜EST1的蚀刻速率大的条件下进行用于在第一层间绝缘膜INS1上形成第一接触孔VG1的蚀刻。接下来，实施蚀刻用于在膜厚比第一层间绝缘膜INS1小的第一蚀刻阻挡膜EST1上形成第一接触孔VG1，由此能够减少半导体衬底SUB的削减。
在第一层间绝缘膜INS1以及第一插塞式电极M1V上，依次形成有作为绝缘膜的第二蚀刻阻挡膜EST2和作为绝缘膜的第二层间绝缘膜INS2。第二蚀刻阻挡膜ST2由氮化硅膜形成，第二层间绝缘膜INS2例如由介电常数在3.0以下的Low－k绝缘膜构成。关于第二层间绝缘膜INS2，具体来说是SiCOH，作为其以外的膜，是有机聚合物膜(聚芳撑、苯并环丁烯、聚酰亚胺等)、帕利灵(注册商标)或BCN(氮化硼碳)膜等。在第二蚀刻阻挡膜EST2和第二层间绝缘膜INS2上，设置有多个第一配线槽WG1，在第一配线槽WG1内，形成有由金属导体膜形成的第一配线M1W。第一配线M1W是由钛(Ti)、氮化钛(TiN)膜、钽(Ta)膜及氮化钽(TaN)膜的一个或多个的层叠膜和铜(Cu)膜的层叠构造形成的铜(Cu)配线。铜膜以铜为主要成分，但也可以含有铝(Al)、锰(Mn)或钯(Pd)等添加物。钛(Ti)、氮化钛(TiN)膜、钽(Ta)膜以及氮化钽(TaN)膜的一个或多个的层叠膜位于铜(Cu)膜与第二层间绝缘膜INS2之间，具有防止铜(Cu)向第二层间绝缘膜INS2内扩散的作用。即，是上述导电性阻隔膜。第一配线M1W与第一插塞式电极M1V电连接。
以覆盖第一配线M1W以及第二层间绝缘膜INS2的方式依次形成有作为绝缘膜的第一绝缘性阻挡膜BR1以及作为绝缘膜的第三层间绝缘膜INS3。第一绝缘性阻挡膜BR1由氮化硅膜或碳氮化硅薄膜(SiCN薄膜)或它们的层叠膜形成。第一绝缘性阻挡膜BR1具有防止构成第一配线M1W的铜(Cu)向第三层间绝缘膜INS3内扩散的作用。即，是上述的绝缘性阻挡膜。另外，第三层间绝缘膜INS3由与第二层间绝缘膜INS2同样的材料构成，例如由SiCOH形成。
在第三层间绝缘膜INS3上，设置有多个第二配线槽WG2，在第二配线槽WG2内形成有由金属导体膜形成的第二配线M2W。以与第一配线槽WG1相连的方式，在第三层间绝缘膜INS3以及第一阻挡膜BR1上形成有第二接触孔VG2，在第二接触孔VG2内设置有由金属导体膜形成的第二插塞式电极M2V。第二配线M2W以及第二插塞式电极M2V由铜(Cu)配线一体地构成，其中该铜(Cu)配线由钛(Ti)、氮化钛(TiN)膜、钽(Ta)膜及氮化钽(TaN)膜的一个或多个的层叠膜和铜(Cu)膜的层叠构造形成。钛(Ti)、氮化钛(TiN)膜、钽(Ta)膜及氮化钽(TaN)膜的一个或多个的层叠膜位于铜(Cu)膜与第三层间绝缘膜INS3之间，具有防止铜(Cu)向第三层间绝缘膜INS3内扩散的作用。即，是上述的导电性阻隔膜。铜膜以铜为主要成分，但也可以含有铝(Al)、锰(Mn)或钯(Pd)等添加物。第二配线M2W经由第二插塞式电极M2V与第一配线M1W电连接。以覆盖第二配线M2W以及第三层间绝缘膜INS3的方式形成有作为绝缘膜的第二绝缘性阻挡膜BR2。第二绝缘性阻挡膜BR2由氮化硅膜以及碳氮化硅薄膜(SiCN薄膜)的单层膜或层叠膜等形成。
在本实施方式中，仅示出了作为第一层配线的第一配线M1W以及作为第二层配线的第二配线M2W，但也可以在第二配线M2W上进一步形成配线。
以下，使用在图1中用虚线包围的部分来说明本实施方式。
图2至图6以及图8至图13是本实施方式的半导体器件的制造工序中的主要部分剖视图。图7是SiN/SiCOH层叠构造的基于飞行时间二次离子质谱法(TOF－SIMS：Time Of Flight Secondary IonMass Spectrometry)的CN－强度的纵深分布图，图14是表示TOF－SIMS的SiCOH膜的主体中的CN－强度与SiN附近的SiCOH表层部中的CN－强度之比、和实际的同层配线间的TDDB寿命之间的关系的图表。以下，同时参照图1来说明本实施方式的半导体器件的制法。图2是说明第二层间绝缘膜INS2以及第一绝缘膜INS21的形成工序的图。准备形成有N型MISFETQn以及P型MISFETQp的半导体衬底SUB，以覆盖N型MISFETQn以及P型MISFETQp的方式在半导体衬底SUB上形成由绝缘膜构成的第一层间绝缘膜INS1。接下来，以使N型MISFETQn的源极区域NSD及漏极区域NSD、以及P型MISFETQp的源极区域PSD及漏极区域PSD露出的方式，在第一层间绝缘膜INS1上形成第一接触孔VG1。接下来，在第一接触孔VG1内形成第一插塞式电极M1V。接下来，如图2所示，在第一插塞式电极M1V以及第一层间绝缘膜INS1上依次形成由绝缘膜形成的第二蚀刻阻挡膜EST2、由绝缘膜形成的第二层间绝缘膜INS2以及由绝缘膜形成的第一绝缘膜INS21。构成第二层间绝缘膜INS2的SiCOH膜能够通过使用了有机硅烷气体(3MS：三甲基硅烷，4MS：四甲基硅烷,1MS：单甲基硅烷，2MS：二甲基硅烷)以及氧化气体(O2、N2O、CO、CO2等)的CVD法来形成。第一绝缘膜INS21是与第二层间绝缘膜INS2相比介电常数高且机械强度大的膜，例如，能够使用氧化硅膜或介电常数高于第二层间绝缘膜INS2且加工耐性出色的SiCOH膜。第一绝缘膜INS21的膜厚小于第二层间绝缘膜INS2的模厚。
图3是说明第一配线槽WG1的形成工序的图。在第一绝缘膜INS21上形成具有与第一配线M1W的图案对应的开口部的由绝缘膜形成的第一抗蚀膜PR1。以第一抗蚀膜PR1为掩膜对第一绝缘膜INS21、第二层间绝缘膜INS2上实施干法刻蚀，形成第一配线槽WG1。该干法刻蚀以相对于第二蚀刻阻挡膜EST2，第二层间绝缘膜INS2以及第一绝缘膜INS21的蚀刻速率较高(大)的条件实施。第一配线槽WG1不仅形成在第二层间绝缘膜INS2上，也形成在第一绝缘膜INS21上形成。另外，第一配线槽WG1的截面形状是第一配线槽WG1的上部开口直径比第一配线槽WG1的底部开口直径宽的锥形状。即，相邻的第一配线槽WG1之间的第一绝缘膜INS21以及第二层间绝缘膜INS2的宽度是上部比底部窄的形状。
图4是说明第一配线M1W的形成工序的图。首先，除去第一抗蚀膜PR1，其后，通过整面蚀刻来蚀刻第二蚀刻阻挡膜EST2，露出第一插塞式电极M1V的上表面。其后，在第一配线槽WG1内依次形成作为导电性膜的第一导电性阻隔膜CBR1以及作为导电性膜的第一铜膜CU1后，对半导体衬底SUB的表面实施CMP处理。而且，仅在第一配线槽WG1内选择性地残留第一导电性阻隔膜CBR1以及第一铜膜CU1，除去第二层间绝缘膜INS2上的第一导电性阻隔膜CBR1以及第一铜膜CU1，由此形成第一配线M1W。在该CMP处理中，也除去第一绝缘膜INS21，得到图4所示的构造。通过在相邻的第一配线M1W间仅残留第二层间绝缘膜INS2，相邻的第一配线M1W间通过Low－k绝缘膜而电分离，因此能够降低第一配线M1W间的电容。
图5是对氨等离子体处理工序进行说明的图。对第一配线M1W以及第二层间绝缘膜INS2的表面实施包含氨(NH3)气的等离子体处理。氨等离子体处理使用NH3气，在压力：1.0～8.0Torr、高频功率：50W～500W、时间：3Sec～100Sec的条件下实施。也可以在NH3气中添加N2气。通过氨等离子体处理，能够除去在CMP处理中在构成第一配线M1W的第一铜膜CU1的表面形成的氧化膜(CuO)，并能够将第二层间绝缘膜INS2的表面改性(例如，掩埋悬挂键(dangling bond))。因此，能够提高在接下来的工序中形成的第一绝缘性阻挡膜BR1与第一配线M1W的粘接性(贴紧性)。然而，由于第二层间绝缘膜INS2由Low－k膜构成，所以通过该氨等离子体处理，在第二层间绝缘膜INS2的表面上形成第一损伤层DM1。第一损伤层DM1形成在从第二层间绝缘膜INS2的表面至深度4nm的范围内。第一损伤层DM1是构成第二层间绝缘膜INS2的SiCOH膜被氮化而成的膜。在本实施方式中，通过氨等离子体处理，在第一损伤层DM1的下部形成第一电场缓和层ER1。第一电场缓和层ER1也是构成第二层间绝缘膜INS2的SiCOH膜被氮化而成的膜。即，第一损伤层DM1和第一电场缓和层ER1是氮浓度高于第二层间绝缘膜INS2的区域。在图5中，为便于理解而将第一损伤层DM1和第一电场缓和层ER1区分表示，但实际上两者是一体的。
图6是对第一绝缘性阻挡膜BR1的形成工序进行说明的图。以覆盖通过氨等离子体处理而被除去了氧化膜(CuO)的第一配线M1W表面以及第二层间绝缘膜INS2表面的方式，形成由绝缘膜形成的第一绝缘性阻挡膜BR1。
图7是表示假定图6的A－A部分的基于TOF－SIMS的CN－强度(氮浓度)分布的图表。是通过TOF－SIMS法对从第一绝缘性阻挡膜BR1到第二层间绝缘膜INS2的规定深度为止进行分析的结果，使用CN－强度表示氮浓度。第二层间绝缘膜INS2的深度方向上的氮浓度在深于表面的位置具有浓度峰值。浓度峰值位于距离第二层间绝缘膜INS2的表面5nm～20nm的范围。第二层间绝缘膜INS2的表面部分(0～4nm)为第一损伤层DM1，具有比表面部分的氮浓度高的氮浓度的区域为第一电场缓和层ER1。在第一电场缓和层ER1中存在氮浓度逐渐增加的区域、氮浓度的峰值区域以及氮浓度逐渐减少的区域。第一电场缓和层ER1的氮浓度高于第一损伤层DM1的氮浓度。换句话说，第一电场缓和层ER1的介电常数高于第一损伤层DM1的介电常数。这样，在相邻的第一配线M1W之间，在比第二层间绝缘膜INS2的表面(上表面)深的位置设有介电常数比表面的介电常数高的区域(层)，由此能够缓和第二层间绝缘膜INS2表面上的电场。其结果，能够提高相邻的第一配线M1W间的TDDB特性(寿命)。若第一电场缓和层ER1距离第二层间绝缘膜INS2表面过远则电场缓和效果减少，因此第一电场缓和层ER1的氮浓度峰值位置最好比第一配线M1W的厚度的1/2浅。
图8是对第三层间绝缘膜INS3、第二绝缘膜INS31以及第二接触孔VG2的形成工序进行说明的图。在第一绝缘性阻挡膜BR1上依次形成第三层间绝缘膜INS3、第二绝缘膜INS31。第三层间绝缘膜INS3以及第二绝缘膜INS31由与第二层间绝缘膜INS2以及第一绝缘膜INS21相同的膜构成。接下来，在第二绝缘膜INS31上形成由具有与第二接触孔VG2对应的开口的绝缘膜形成的第二抗蚀膜PR2。如图8所示，将该第二抗蚀膜PR2用作掩膜，对第二绝缘膜INS31、第三层间绝缘膜INS3实施干法刻蚀，来形成第二接触孔VG2。在第一绝缘性阻挡膜BR1上停止蚀刻。因此，在第二接触孔VG2的底部残留有第一绝缘性阻挡膜BR1。
接下来，图9是对用于形成第二配线槽WG2的由绝缘膜形成的第4抗蚀膜PR4的形成工序说明的图。在除去第二抗蚀膜PR2后，在第二接触孔VG2内以及第二绝缘膜INS31上形成第三抗蚀膜PR3。在第三抗蚀膜PR3上形成第三绝缘膜INS32以及由绝缘膜形成的防反射膜BARC。第三绝缘膜INS32由氧化硅膜形成，通过低温CVD法形成。接下来，在防反射膜BARC上形成具有与第二配线槽WG2对应的开口的第4抗蚀膜PR4。
图10是对形成第二配线槽WG2的工序进行说明的图。以第4抗蚀膜PR4为掩膜，对第二绝缘膜INS31以及第三层间绝缘膜INS3实施干法刻蚀，形成第二配线槽WG2。此时，同时除去在第三抗蚀膜PR3之上形成的第三绝缘膜INS32、防反射膜BARC以及第4抗蚀膜PR4，如图10所示，在第二配线槽WG2的周围以及第二接触孔VG2内残留第三抗蚀膜PR3。
图11是对除去第一阻挡膜BR1的工序进行说明的图。首先，除去残留在第二配线槽WG2的周围以及第二接触孔VG2内的第三抗蚀膜PR3，其后，为了去掉BR1的开口部，通过实施整面蚀刻，如图11所示，使第一配线M1W的表面露出。在该整面蚀刻的工序中，第二绝缘膜INS31也被蚀刻而变薄。
图12是对形成第二配线M2W的工序进行说明的图。在第二接触孔VG2以及第二配线槽WG2内，依次形成作为导电性膜的第二导电性阻隔膜CBR2以及作为导电性膜的第二铜膜CU2后，对第二铜膜CU2的表面实施CMP处理。而且，仅在第二接触孔VG2内以及第二配线槽WG2内选择性地残留第二导电性阻隔膜CBR2以及第二铜膜CU2，以形成第二配线M2W。在该CMP处理中，也除去第二绝缘膜INS31，使第三层间绝缘膜INS3的表面露出，由此，第二配线M2W之间通过Low－k绝缘膜电分离，从而能够降低第二配线M2W间的电容。
图13是说明氨等离子体处理的工序和第二绝缘性阻挡膜BR2的形成工序的图。对第二配线M2W以及第三层间绝缘膜INS3的表面实施含有氨(NH3)气的等离子体处理。氨等离子体处理的条件与第一配线M1W的情况相同。通过该氨等离子体处理，在第三层间绝缘膜INS3的表面形成第二损伤层DM2。第二损伤层DM2形成在从第三层间绝缘膜INS3表面至深度4nm的范围内。第二损伤层DM2是构成第三层间绝缘膜INS3的SiCOH膜被氮化而成的膜。在本实施方式中，通过氨等离子体处理，在第二损伤层DM2的下部形成第二电场缓和层ER2。第二电场缓和层ER2也是构成第三层间绝缘膜INS3的SiCOH膜被氮化而成的膜。即，第二损伤层DM2和第二电场缓和层ER2是氮浓度高于第三层间绝缘膜INS3的区域。在图13中，为了便于理解而将第二损伤层DM2和第二电场缓和层ER2区分表示，但实际上两者是一体的。接下来，以覆盖第三层间绝缘膜INS3以及第二配线M2W的方式形成由绝缘膜形成的第二绝缘性阻挡膜BR2，得到图13的构造。图13的B－B部分的氮浓度分布与图7所示的图表相同。第二电场缓和层ER2由与第一电场缓和层ER1同样的构成形成，因此第二电场缓和层ER2起到与第一电场缓和层ER1同样的效果。因为冗长而省略重复的说明，能够理解为在图7的说明段落的记述中将第二层间绝缘膜INS2换为第三层间绝缘膜INS3、第一损伤层DM1换为第二损伤层DM2、第一电场缓和层ER1换为第二电场缓和层ER2、第一配线M1W换为第二配线M2W。
图14是说明本实施方式的效果的图表。图14表示构成层间绝缘膜的SiCOH膜的内部与表面的CN－强度比(氮浓度比)、和TDDB寿命之间的关系。若CN－强度比为1以上，则TDDB寿命提高一个数量级以上。即，通过在层间绝缘膜的内部设置氮浓度比表面的氮浓度高的层，TDDB寿命提高一个数量级以上。换句话说，通过设置氮浓度比第一损伤层DM1的氮浓度高的第一电场缓和层ER1，相邻的第一配线M1W间的TDDB寿命提高一个数量级以上。同样地，通过设置第二电场缓和层ER2，相邻的第二配线M2W间的TDDB寿命提高一个数量级以上。
(实施方式2)
本实施方式2是上述实施方式1的变形例，与实施方式1相比，第一电场缓和层ER1以及第二电场缓和层ER2的形成方法和氨等离子体处理的条件不同，其他部分相同。在本实施方式2中，第一电场缓和层ER1在第二层间绝缘膜INS2的形成工序中形成，第二电场缓和层ER2在第三层间绝缘膜INS3的形成中形成。因此，通过氨等离子体处理工序形成第一损伤层DM1以及第二损伤层DM2，但不形成第一电场缓和层ER1以及第二电场缓和层ER2。图15是表示第二层间绝缘膜INS2以及第三层间绝缘膜INS3形成时的气体流动的图，图16是表示图6的A－A部分以及图13的B－B部分的基于飞行时间二次离子质谱仪(TOF－SIMS)测得的CN－强度(氮浓度)分布的图表。
构成第二层间绝缘膜INS2的SiCOH膜通过使用了有机硅烷气体(3MS：三甲基硅烷，4MS：四甲基硅烷,1MS：单甲基硅烷，2MS：二甲基硅烷)以及氧化气体(O2、N2O、CO、CO2等)的CVD法形成。在本实施方式2中，具有如下特征：在规定的定时添加包含氮的气体(N2、NH3等)。其他的CVD条件为300～400℃的范围、压力为1.0～8.0Torr、高频功率为100W～500W的范围。如图15所示，在稳定的压力下，流通有机硅烷气体、氧(O2)气，同时施加功率。在CVD成长的后半阶段添加氨(NH3)气并慢慢地提高流量，在流量达到设定值后使其慢慢地下降，并归零。其后，切断有机硅烷气体、氧(O2)气，同时切断功率。通过实施像以上那样的氨(NH3)气的流动，能够使膜中的氮浓度呈现阶段状。通过这样的制法，能够在比第二层间绝缘膜INS2的表面深的位置形成第一电场缓和层ER1。通过将该制法也适用于第三层间绝缘膜INS3，能够在形成第三层间绝缘膜INS3时，在比第三层间绝缘膜INS3的表面深的位置形成第二电场缓和层ER2。对第二层间绝缘膜INS2以及第三层间绝缘膜INS3的表面实施氨等离子体处理的条件与实施方式1不同。由氨等离子体处理产生的第一损伤层DM1以及第二损伤层DM2的氮浓度最好比形成第二层间绝缘膜INS2以及第三层间绝缘膜INS3时的电场缓和层ER1、ER2的氮浓度小。例如期望在氨等离子体处理时添加氢气。
根据本实施方式2，能够实现与实施方式1的图6以及图13中所说明的构造相同的构造。但是，通过本实施方式2而得的图6的A－A部分以及图13的B－B部分的CN－强度(氮浓度)如图16所示。例如虽然以图6的A－A部分为例进行说明，但在图13的B－B部分也能得到同样的效果。与实施方式1的情况同样地，在第一电场缓和层ER1上存在氮浓度逐渐增加的区域、氮浓度的峰值区域以及氮浓度逐渐减少的区域。第一电场缓和层ER1的氮浓度高于第一损伤层DM1的氮浓度。换句话说，第一电场缓和层ER1的介电常数高于第一损伤层DM1的介电常数。
因为第一电场缓和层ER1在与第一损伤层DM1不同的工序中形成，所以能够减少第二层间绝缘膜INS2表面的因氨等离子体处理而引起的损伤，从而与实施方式1相比，能够提高相邻的第一配线M1W间的TDDB寿命。另外，容易控制第二层间绝缘膜INS2内的第一电场缓和层ER1的位置即氮浓度峰值。氮浓度在比第一绝缘性阻挡膜BR1与第二层间绝缘膜INS2的界面深的位置具有峰值是指，在此处介电常数变高，电场在第一绝缘性阻挡膜BR1与第二层间绝缘膜INS2的界面处不会集中。其结果，能够改善配线间TDDB。
图17是表示本实施方式2的、第二层间绝缘膜INS2的形成方法的变形例的气体流动的图。也能够适用于第三层间绝缘膜INS3。具有如下特征：代替添加氨气，而是使O2气的流量变化。如图17所示，在稳定的压力下，流通有机硅烷气、氧(O2)气，同时施加高频功率。在CVD成长的后半阶段，进一步慢慢地提高氧(O2)气流量，在氧气流量达到设定值后使其慢慢地下降，并返回原来的设定值。其后，流通有机硅烷气体、氧(O2)气并同时切断功率。通过实施像以上那样的流动，能够使膜中的氧浓度呈现阶段状。通过这样的制法，能够在比第二层间绝缘膜INS2的表面深的位置形成第一电场缓和层ER1。该制法也适用于第三层间绝缘膜INS3，其结果，能够形成具有实施方式1的图13的构造的半导体器件。但是，第一电场缓和层ER1由具有比第二层间绝缘膜INS2的氧浓度高的氧浓度的层构成，这一点与实施方式1不同。因为第一电场缓和层ER1的介电常数高于第二层间绝缘膜INS2的介电常数，所以在比第二层间绝缘膜INS2的表面深的位置，配置具有比第二层间绝缘膜INS2的介电常数高的介电常数的第一电场缓和层ER1，由此能够缓和相邻的第一配线M1W间的第二层间绝缘膜INS2表面的电场。其结果，能够提高相邻的第一配线M1W间的TDDB寿命。第一电场缓和层ER1的氧浓度峰值位置最好比第一配线M1W的厚度的1/2浅。第二电场缓和层ER2的氧浓度峰值位置也最好比第二配线M2W的厚度的1/2浅。
(实施方式3)
本实施方式3是上述实施方式2的变形例，与实施方式2相比，第一电场缓和层ER1以及第二电场缓和层ER2的形成方法不同，其他的部分相同。在本实施方式3中，第一电场缓和层ER1在第二层间绝缘膜INS2的形成工序后形成，第二电场缓和层ER2在第三层间绝缘膜INS3形成后形成。即，在形成第二层间绝缘膜INS2后，在距离第二层间绝缘膜INS2的表面规定深度的位置实施氮离子注入，由此，在比第二层间绝缘膜INS2的表面深的位置形成第一电场缓和层ER1。在第三层间绝缘膜INS3中也能够适用同样的方法。
根据本实施方式3，能够实现与实施方式1的图6以及图13中说明的构造同样的构造。图18是表示图6的A－A部分以及图13的B－B部分的基于飞行时间二次离子质谱仪(TOF－SIMS)测得的CN－强度(氮浓度)分布的图表。例如，在比第二层间绝缘膜INS2表面的第一损伤层DM1深的位置，存在具有比第一损伤层DM1的氮浓度高的氮浓度的第一电场缓和层ER1。在第一电场缓和层ER1内存在氮浓度的峰值部分。相比于实施方式2，具有氮元素的深度方向和浓度控制优异的优点。在图13的B－B部分也能得到同样的效果。
(实施方式4)
本实施方式4是上述实施方式1的变形例，具有以下的不同点。首先，第一绝缘性阻挡膜BR1由第一辅助绝缘性阻挡膜BR11和第二辅助绝缘性阻挡膜BR12构成，第二绝缘性阻挡膜BR2由第一辅助绝缘性阻挡膜BR21和第二辅助绝缘性阻挡膜BR22构成。未形成第二层间绝缘膜INS2内的第一电场缓和层ER1以及第三电场缓和层INS3内的第二电场缓和层2。
图19是本实施方式4的半导体器件的主要部位截面构造。使用覆盖第一配线M1W的第一绝缘性阻挡膜BR1进行说明。第一绝缘性阻挡膜BR1由覆盖第一配线M1W的第一辅助绝缘性阻挡层BR11、和形成在第一辅助绝缘性阻挡层BR11上的第二辅助绝缘性阻挡层BR12构成。第二辅助绝缘性阻挡层BR12具有比第一辅助绝缘性阻挡层BR11的氮浓度高的氮浓度。特别地，第二辅助绝缘性阻挡层BR12具有比第一辅助绝缘性阻挡层BR11的下表面(与第一配线M1W的界面)处的氮浓度高的氮浓度。在图19中，为了便于理解而将第一辅助绝缘性阻挡层BR11和第二辅助绝缘性阻挡层BR12区分表示，但实际上两者是一体的。
图20是表示图19的A－A部分的基于飞行时间二次离子质谱仪(TOF－SIMS)测得的CN－强度(氮浓度)分布的图表。与下述界面处的氮浓度相比，该界面是指位于第一配线M1W间的第二层间绝缘膜INS2和在其上形成的第一绝缘性阻挡膜BR1的界面，远离界面的位置处的第一绝缘性阻挡膜BR1的氮浓度较高。即，在远离界面的位置上存在第二辅助绝缘性阻挡层BR12。第一绝缘性阻挡膜BR1的氮浓度随着远离第二层间绝缘膜INS2与在其上形成的第一绝缘性阻挡膜BR1的界面而增加。
第一绝缘性阻挡膜BR1例如使用SiCN膜。SiCN膜例如由CVD法形成，在温度为300～400℃的范围、压力为1.0～8.0Torr、高频功率为50W～1000W的范围的条件下使用。气体使用有机硅烷、SiH4、氨(NH3)、CO、CO2、N2O等。图21是使用有机硅烷气体和氨(NH3)气来形成构成第一绝缘性阻挡膜BR1的SiCN膜时的气体流动图。在稳定的压力下，流通有机硅烷气体、氨(NH3)气，同时施加功率。在CVD成长的最后阶段，使氨(NH3)气从原来的流量进一步慢慢地上升，在流量达到设定值后使其慢慢地下降，返回原来的设定值。其后，同时切断有机硅烷气体、氨(NH3)气以及功率。通过实施以上那样的氨(NH3)气的流动，能够使第一绝缘性阻挡膜BR1中的氮浓度呈阶段状。
和下述界面处的氮浓度相比，该界面是指位于第一配线M1W间的第二层间绝缘膜INS2与在其上形成的第一绝缘性阻挡膜BR1的界面，通过使远离界面的位置处的第一绝缘性阻挡膜BR1的氮浓度较高，能够使相邻的第一配线M1W间的TDDB寿命提高。这是因为，通过在远离界面的位置在第一绝缘性阻挡膜BR1中设置氮浓度高的区域，能够缓和界面部分处的相邻的第一配线M1W间的电场。
图22是表示图19的A－A部分的基于飞行时间二次离子质谱仪(TOF－SIMS)测得的CN－强度(氮浓度)分布的图表。是图20中说明的例子的变形例。在形成于第一辅助绝缘性阻挡层BR11上的第二辅助绝缘性阻挡层BR12内，存在具有氮浓度峰值的区域，对于氮浓度的峰值来说，期望是在距离第一绝缘性阻挡膜BR1的下表面5～40nm的范围内具有氮浓度峰值。第二绝缘性阻挡膜BR2也具有同样的构造和同样的效果。若在一个膜中具有氮浓度峰值，则与界面具有峰值的情况相比，耐破坏性也强，因此优选该构造。
以上，基于实施方式具体地说明了本发明的发明人完成的发明，但是本发明并不限定于上述实施方式，当然也能够在不超出其主旨的范围内进行种种变更或适当组合实施方式。例如，能够在实施方式1～3中组合实施方式4。
此外，在本申请中，也包含下述的发明。
一种半导体器件的制造方法，具有：
工序(a)，准备半导体衬底；
工序(b)，在上述半导体衬底上形成具有第一主面且具有规定膜厚的层间绝缘膜；
工序(c)，在上述层间绝缘膜的上述第一主面上形成第一配线槽以及第二配线槽；
工序(d)，在上述第一配线槽以及第二配线槽内选择性地设置铜膜以形成第一配线以及第二配线；以及
工序(e)，对上述第一配线、上述第二配线以及上述层间绝缘膜的上述第一主面实施含有氨的等离子体处理，
在上述工序(e)中，在上述层间绝缘膜的上述第一主面上形成损伤层，并在上述损伤层的下方形成电场缓和层，
上述损伤层以及上述电场缓和层的氮浓度大于上述层间绝缘膜的氮浓度，上述电场缓和层的氮浓度大于上述损伤层的氮浓度。
附图标记说明
BARC  防反射膜
BR1、BR2  绝缘性阻挡膜
BR11、BR12、BR21、BR22  辅助绝缘性阻挡层
CU1、CU2  铜膜
CBR1、CBR2  导电性阻隔膜
DM1、DM2  损伤层
ER1、ER2  电场缓和层
EST1、EST2  蚀刻阻挡膜
INS1、INS2、INS3  层间绝缘膜
INS21、INS31、INS32  绝缘膜
M1W、M2W  配线
M1V、M2V  插塞式电极
NCH、PCH  沟道区域
NG、PG  栅电极
NGI、PGI  栅极绝缘膜
NSD、PSD  源极区域或漏极区域
NW N  型阱区域
PR1、PR2、PR3、PR4  抗蚀膜
PW P  型阱区域
Qn N  型MISFET
Qp P  型MISFET
SUB P  型半导体衬底
SIL  硅化物膜
ST  元件分离膜
VG1、VG2  接触孔
WG1、WG2  配线槽

Claims (20)

1.一种半导体器件，具有：
半导体衬底；
形成在所述半导体衬底上且具有主面的层间绝缘膜；
埋入所述层间绝缘膜内且彼此相邻的第一配线以及第二配线；
位于所述第一配线与所述第二配线之间且形成在所述层间绝缘膜的所述主面上的损伤层；以及
在所述损伤层的下方，形成在所述层间绝缘膜上的电场缓和层，所述第一配线和所述第二配线主要由铜膜形成，
所述损伤层和所述电场缓和层是含氮层，所述电场缓和层的氮浓度大于所述损伤层的氮浓度。
2.根据权利要求1所述的半导体器件，其中，
所述层间绝缘膜由介电常数为3.0以下的绝缘膜形成。
3.根据权利要求2所述的半导体器件，其中，
所述层间绝缘膜由SiCOH膜形成。
4.根据权利要求1所述的半导体器件，其中，
所述损伤层存在于从所述层间绝缘膜的所述主面至深度4nm的范围内。
5.根据权利要求1所述的半导体器件，其中，
所述电场缓和层具有氮浓度的峰值区域。
6.根据权利要求5所述的半导体器件，其中，
所述氮浓度的峰值区域位于距离所述层间绝缘膜的所述主面5～20nm的范围内。
7.根据权利要求1所述的半导体器件，其中，
所述电场缓和层设置于以所述层间绝缘膜的所述主面为基准，比所述第一配线的厚度的1/2浅的位置。
8.一种半导体器件，具有：
半导体衬底；
形成在所述半导体衬底上且具有第一主面的层间绝缘膜；
埋入所述层间绝缘膜内且彼此相邻的第一配线以及第二配线；
位于所述第一配线与所述第二配线之间且形成在所述层间绝缘膜的所述第一主面上的损伤层；以及
与所述第一配线、所述第二配线以及损伤层接触，并将所述第一配线、所述第二配线以及所述层间绝缘膜覆盖的绝缘性阻挡膜，
所述第一配线和所述第二配线主要由铜膜形成，
所述绝缘性阻挡膜是含氮的绝缘膜，且具有与所述损伤层接触的第一表面和与所述第一表面相反一侧的第二表面，所述绝缘性阻挡膜具有氮浓度高于所述第一表面的氮浓度的第一区域。
9.根据权利要求8所述的半导体器件，其中，
所述氮浓度高的第一区域位于所述第二表面侧。
10.根据权利要求8所述的半导体器件，其中，
所述绝缘性阻挡膜的氮浓度从所述第一表面朝向所述第二表面而增加。
11.根据权利要求8所述的半导体器件，其中，
所述层间绝缘膜由介电常数为3.0以下的绝缘膜形成。
12.根据权利要求11所述的半导体器件，其中，
所述层间绝缘膜由SiCOH膜形成。
13.根据权利要求8所述的半导体器件，其中，
在所述损伤层的下方，在所述层间绝缘膜内具有电场缓和层。
14.根据权利要求13所述的半导体器件，其中，
所述损伤层和所述电场缓和层是含氮层，所述电场缓和层的氮浓度大于所述损伤层的氮浓度。
15.一种半导体器件的制造方法，具有：
工序(a)，准备半导体衬底；
工序(b)，在所述半导体衬底上形成具有第一主面且具有规定膜厚的层间绝缘膜；
工序(c)，在所述层间绝缘膜的所述第一主面上形成第一配线槽以及第二配线槽；
工序(d)，在所述第一配线槽以及第二配线槽内选择性地设置铜膜，形成第一配线以及第二配线；以及
工序(e)，对所述第一配线、所述第二配线以及所述层间绝缘膜的所述第一主面实施含有氨的等离子体处理，
在所述工序(b)中，在所述层间绝缘膜上，在比所述第一主面深的位置设置电场缓和层，
在所述工序(e)中，在所述层间绝缘膜的所述第一主面上形成损伤层。
16.根据权利要求15所述的半导体器件的制造方法，其中，
所述电场缓和层和所述损伤层是氮浓度大于所述层间绝缘膜的层。
17.根据权利要求16所述的半导体器件的制造方法，其中，
所述电场缓和层是通过在形成所述层间绝缘膜后、向所述层间绝缘膜内离子注入氮而形成的。
18.根据权利要求16所述的半导体器件的制造方法，其中，
所述层间绝缘膜由SiCOH膜形成，所述SiCOH膜通过使用了有机硅烷气体以及氧化气体的CVD法形成，
通过在所述SiCOH膜形成工序的中途添加氨气，在所述SiCOH膜内形成所述电场缓和层。
19.根据权利要求15所述的半导体器件的制造方法，其中，
所述层间绝缘膜由SiCOH膜形成，所述SiCOH膜通过使用了有机硅烷气体以及氧化气体的CVD法形成，
通过在所述SiCOH膜形成工序的中途增加氧系气体的流量，在所述SiCOH膜内形成所述电场缓和层。
20.根据权利要求15所述的半导体器件的制造方法，其中，
在所述工序(e)之后，还具有
工序(f)，即，在所述层间绝缘膜上形成具有第一表面和第二表面的绝缘性阻挡膜，所述第一表面与所述第一配线、所述第二配线以及所述损伤层接触，所述第二表面为与所述第一表面相反一侧，
所述绝缘性阻挡膜的所述第二表面的氮浓度大于所述第一表面的氮浓度。
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