JPWO2013057867A1 - 半導体装置 - Google Patents
半導体装置 Download PDFInfo
- Publication number
- JPWO2013057867A1 JPWO2013057867A1 JP2013539505A JP2013539505A JPWO2013057867A1 JP WO2013057867 A1 JPWO2013057867 A1 JP WO2013057867A1 JP 2013539505 A JP2013539505 A JP 2013539505A JP 2013539505 A JP2013539505 A JP 2013539505A JP WO2013057867 A1 JPWO2013057867 A1 JP WO2013057867A1
- Authority
- JP
- Japan
- Prior art keywords
- wiring
- semiconductor device
- substrate
- semiconductor chip
- boundary line
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
- H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
- H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
- H01L25/065—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00
- H01L25/0657—Stacked arrangements of devices
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
- H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
- H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
- H01L23/3114—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed the device being a chip scale package, e.g. CSP
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
- H01L23/49838—Geometry or layout
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
- H01L23/528—Geometry or layout of the interconnection structure
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
- H01L24/19—Manufacturing methods of high density interconnect preforms
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/023—Redistribution layers [RDL] for bonding areas
- H01L2224/0237—Disposition of the redistribution layers
- H01L2224/02375—Top view
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/023—Redistribution layers [RDL] for bonding areas
- H01L2224/0237—Disposition of the redistribution layers
- H01L2224/02379—Fan-out arrangement
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/0401—Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/04042—Bonding areas specifically adapted for wire connectors, e.g. wirebond pads
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/04105—Bonding areas formed on an encapsulation of the semiconductor or solid-state body, e.g. bonding areas on chip-scale packages
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/0554—External layer
- H01L2224/0556—Disposition
- H01L2224/05569—Disposition the external layer being disposed on a redistribution layer on the semiconductor or solid-state body
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/0554—External layer
- H01L2224/0556—Disposition
- H01L2224/05571—Disposition the external layer being disposed in a recess of the surface
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
- H01L2224/12105—Bump connectors formed on an encapsulation of the semiconductor or solid-state body, e.g. bumps on chip-scale packages
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
- H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
- H01L2224/13001—Core members of the bump connector
- H01L2224/13099—Material
- H01L2224/131—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
- H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
- H01L2224/13001—Core members of the bump connector
- H01L2224/13099—Material
- H01L2224/131—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
- H01L2224/13138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
- H01L2224/13144—Gold [Au] as principal constituent
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16135—Disposition the bump connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
- H01L2224/16145—Disposition the bump connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73201—Location after the connecting process on the same surface
- H01L2224/73207—Bump and wire connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73265—Layer and wire connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
- H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
- H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
- H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
- H01L2225/06503—Stacked arrangements of devices
- H01L2225/0651—Wire or wire-like electrical connections from device to substrate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
- H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
- H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
- H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
- H01L2225/06503—Stacked arrangements of devices
- H01L2225/06513—Bump or bump-like direct electrical connections between devices, e.g. flip-chip connection, solder bumps
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
- H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
- H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
- H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
- H01L2225/06503—Stacked arrangements of devices
- H01L2225/06527—Special adaptation of electrical connections, e.g. rewiring, engineering changes, pressure contacts, layout
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
- H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
- H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
- H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
- H01L2225/06503—Stacked arrangements of devices
- H01L2225/06555—Geometry of the stack, e.g. form of the devices, geometry to facilitate stacking
- H01L2225/06568—Geometry of the stack, e.g. form of the devices, geometry to facilitate stacking the devices decreasing in size, e.g. pyramidical stack
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
- H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
- H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
- H01L23/3121—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
- H01L23/5389—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates the chips being integrally enclosed by the interconnect and support structures
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/02—Bonding areas ; Manufacturing methods related thereto
- H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L24/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/10—Bump connectors ; Manufacturing methods related thereto
- H01L24/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
- H01L24/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/10—Bump connectors ; Manufacturing methods related thereto
- H01L24/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L24/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L24/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L24/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/42—Wire connectors; Manufacturing methods related thereto
- H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L24/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/73—Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01029—Copper [Cu]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/153—Connection portion
- H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
- H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/153—Connection portion
- H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
- H01L2924/15313—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a land array, e.g. LGA
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/156—Material
- H01L2924/15786—Material with a principal constituent of the material being a non metallic, non metalloid inorganic material
- H01L2924/15787—Ceramics, e.g. crystalline carbides, nitrides or oxides
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/156—Material
- H01L2924/15786—Material with a principal constituent of the material being a non metallic, non metalloid inorganic material
- H01L2924/15788—Glasses, e.g. amorphous oxides, nitrides or fluorides
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
- H01L2924/191—Disposition
- H01L2924/19101—Disposition of discrete passive components
- H01L2924/19107—Disposition of discrete passive components off-chip wires
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Geometry (AREA)
- Manufacturing & Machinery (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Abstract
Description
以下、本発明の実施形態を図を用いて説明する。図1は、本発明の実施形態に係る半導体装置を示す平面図である。また、図2(a)は、図1に示すIIa-IIa線における本実施形態の半導体装置の断面図であり、図2(b)は、図1に示すIIb-IIb線における当該半導体装置の断面図である。
図4は、本発明の実施形態に係る半導体装置の変形例を示す断面図である。同図では、配線34を通り、且つ配線34の延伸方向に平行な方向における断面を示している。
図1、図2(a)、(b)を用いて説明した構成を、ファンアウトWLPタイプの半導体装置に適用した第1の応用例について以下説明する。
図7は、本発明の実施形態の第2の応用例に係る半導体装置を示す平面図である。本応用例に係る半導体装置は、図5又は図6に示すファンアウトWLPを用いたSiP(system in package)である。なお、図7に示す再配線39のうち少なくとも一本は、配線肉厚部39aを有している再配線であってもよいし、図5に示す再配線35、36、37のいずれかと同様に、配線拡幅部、斜行部分、分岐部分を有する形状の再配線であってもよい。また、半導体チップ11上の回路と再配線39とを電気的に接続させるチップ電極は図示していない。
図8(a)は、本発明の実施形態の第3の応用例に係る半導体装置を示す平面図である。また、図8(b)は、本応用例に係る半導体装置のA部を拡大して示す断面図であり、図8(c)は、当該A部を拡大して示す平面図である。図8(a)、(b)で第2の絶縁保護膜42と半導体チップ12との間に示すのは、アンダーフィル材86である。また、図8(c)において、再配線39のうち半導体チップ12の下に設けられた部分は破線で示している。
図9(a)は、本発明の実施形態の第4の応用例に係る半導体装置を示す平面図である。また、図9(b)は、本応用例に係る半導体装置のA部を拡大して示す断面図であり、図9(c)は、当該A部を拡大して示す平面図である。
4 絶縁保護膜
8 境界領域
9、10 非境界領域
11、12 半導体チップ
19 (基材1の)主面
20 (基材2の)主面
21 拡張部材
22 封止樹脂
28 境界線
31、32、33、34、44、46、48 配線
31a、35a 配線拡幅部
32a、36a 部分
33a、33b、37a、37b 分岐部分
34a、38a、39a 配線肉厚部
35、36、37、38、39 再配線
40 凹部
41 第1の絶縁保護膜
42 第2の絶縁保護膜
49 (拡張部材21の)主面
50 (半導体チップ11の)主面
51、52、53、54 チップ電極
55 電極
61、62、63 電極
64、65 電極
71、71a バンプ
81 基板
82 ランド
83 接着剤
86 アンダーフィル材
91 ワイヤ
Claims (17)
- 回路が形成された第1の面を有する第1の基材と、
前記第1の面と同じ方向を向いて前記第1の面に隣接する第2の面を有し、前記第1の基材とは線膨張係数が異なり、前記第1の基材と接する第2の基材と、
前記第1の面上及び前記第2の面上に、平面視における前記第1の基材と前記第2の基材との第1の境界線を跨ぐように設けられ、前記第1の面に形成された回路に接続された第1の配線とを備え、
前記第1の境界線上での前記第1の配線の断面積は、前記第1の配線のうち、前記第1の面上に設けられた部分の少なくとも一部の配線幅方向断面の面積、又は前記第1の配線のうち、前記第2の面上に設けられた部分の少なくとも一部の配線幅方向断面の面積よりも大きい半導体装置。 - 請求項1に記載の半導体装置において、
前記第1の境界線上における前記第1の配線の配線幅は、前記第1の面上における前記第1の配線の少なくとも一部の配線幅、及び前記第2の面上における前記第1の配線の少なくとも一部の配線幅よりも広いことを特徴とする半導体装置。 - 請求項1又は2に記載の半導体装置において、
前記第1の境界線上における前記第1の配線の厚みは、前記第1の面上における前記第1の配線の少なくとも一部の厚み、及び前記第2の面上における前記第1の配線の少なくとも一部の厚みよりも厚いことを特徴とする半導体装置。 - 請求項1〜3のうちいずれか1つに記載の半導体装置において、
前記第1の配線のうち前記第1の境界線上を跨ぐ部分の延伸方向は前記第1の境界線に対して直交しないことを特徴とする半導体装置。 - 請求項1〜4のうちいずれか1つに記載の半導体装置において、
前記第1の配線は、前記第1の境界線上で複数本に分岐していることを特徴とする半導体装置。 - 請求項1〜5のうちいずれか1つに記載の半導体装置において、
前記第1の基材は第1の半導体チップであり、
前記第2の基材は前記第1の半導体チップの側面から外方に設けられた拡張部材であり、
前記第1の面上及び前記第2の面上には絶縁保護膜が設けられており、
前記第1の配線は、前記絶縁保護膜上に設けられていることを特徴とする半導体装置。 - 請求項6に記載の半導体装置において、
前記拡張部材の前記第2の面側には凹部が形成されており、
前記第1の半導体チップは、前記凹部内に配置されていることを特徴とする半導体装置。 - 請求項6又は7に記載の半導体装置において、
前記第1の面及び前記第2の面を上に向けた状態で前記第1の半導体チップ及び前記拡張部材が搭載された上面を有する基板と、
回路が形成された第3の面を前記第1の面に対向させた状態で、前記第1の半導体チップの前記第1の面上に搭載された第2の半導体チップと、
前記第1の半導体チップと前記第2の半導体チップとの間に設けられ、前記第1の面上に形成された回路とを電気的に接続する第1の接続部材と、
前記基板の上面上に設けられ、前記拡張部材の側面及び前記第2の面、前記第2の半導体チップの側面及び前記第3の面に対向する面を覆う封止樹脂とをさらに備えていることを特徴とする半導体装置。 - 請求項8に記載の半導体装置において、
前記第1の配線のうち前記第2の面上に設けられた部分上に設けられた第1の電極と、
前記基板の上面上に設けられた第2の電極と、
前記第1の電極と前記第2の電極とを接続し、前記封止樹脂に覆われた第2の接続部材とをさらに備えている半導体装置。 - 請求項6〜9のうちいずれか1つに記載の半導体装置において、
前記拡張部材は、封止樹脂体、有機基板、セラミック基板、又はガラス基板であることを特徴とする半導体装置。 - 請求項6〜10のうちいずれか1つに記載の半導体装置において、
前記第1の半導体チップと前記拡張部材とは、平面視において前記第1の境界線とは異なる方向に延びる第2の境界線を形成しており、
前記第1の面上及び前記第2の面上には、前記第1の面に形成された回路に電気的に接続され、前記第2の境界線を跨ぐ第2の配線が設けられており、
前記第2の境界線上での前記第2の配線の断面積は、前記第2の配線のうち、前記第1の面上に設けられた部分の少なくとも一部の配線幅方向断面の面積、及び前記第2の配線のうち、前記第2の面上に設けられた部分の少なくとも一部の配線幅方向断面の面積よりも大きいことを特徴とする半導体装置。 - 請求項1〜11のうちいずれか1つに記載の半導体装置において、
前記第1の配線は、前記第1の境界線上に設けられた部分を含む境界領域と、非境界領域とを有し、前記第1の境界線上での前記第1の配線の断面積は、前記第1の面上における前記非境界領域の配線幅方向断面の面積、及び前記第2の面上における前記非境界領域の配線幅方向断面の面積よりも大きいことを特徴とする半導体装置。 - 回路が形成された第1の面を有する第1の基材と、
前記第1の面と同じ方向を向いて前記第1の面に隣接する第2の面を有し、前記第1の基材とは線膨張係数が異なり、前記第1の基材と接する第2の基材と、
前記第1の面上及び前記第2の面上に、平面視における前記第1の基材と前記第2の基材との境界線を跨ぐように設けられ、前記第1の面に形成された回路に電気的に接続された配線とを備え、
前記境界線上における前記配線の厚みは、前記第1の面上における前記配線の少なくとも一部の厚み、又は前記第2の面上における前記配線の少なくとも一部の厚みよりも厚いことを特徴とする半導体装置。 - 回路が形成された第1の面を有する第1の基材と、
前記第1の面と同じ方向を向いて前記第1の面に隣接する第2の面を有し、前記第1の基材とは線膨張係数が異なり、前記第1の基材と接する第2の基材と、
前記第1の面上及び前記第2の面上に、平面視における前記第1の基材と前記第2の基材との境界線を跨ぐように設けられ、前記第1の面に形成された回路に電気的に接続された配線とを備え、
前記配線のうち前記境界線上を跨ぐ部分の延伸方向は前記境界線に対して直交しないことを特徴とする半導体装置。 - 回路が形成された第1の面を有する第1の基材と、
前記第1の面と同じ方向を向いて前記第1の面に隣接する第2の面を有し、前記第1の基材とは線膨張係数が異なり、前記第1の基材と接する第2の基材と、
前記第1の面上及び前記第2の面上に、平面視における前記第1の基材と前記第2の基材との境界線を跨ぐように設けられ、前記第1の面に形成された回路に電気的に接続された配線とを備え、
前記配線は、前記境界線上で複数本に分岐していることを特徴とする半導体装置。 - 請求項13〜15のうちいずれか1つに記載の半導体装置において、
前記第1の基材は第1の半導体チップであり、
前記第2の基材は前記第1の半導体チップの側面から外方に設けられた拡張部材であり、
前記第1の面上及び前記第2の面上には絶縁保護膜が設けられており、
前記第1の配線は、前記絶縁保護膜上に設けられていることを特徴とする半導体装置。 - 請求項16に記載の半導体装置において、
前記第1の面及び前記第2の面を上に向けた状態で前記第1の半導体チップ及び前記拡張部材が搭載された上面を有する基板と、
回路が形成された第3の面を前記第1の面に対向させた状態で、前記第1の半導体チップの前記第1の面上に搭載された第2の半導体チップと、
前記第1の半導体チップと前記第2の半導体チップとの間に設けられ、前記第1の面上に形成された回路とを電気的に接続する接続部材と、
前記基板の上面上に設けられ、前記拡張部材の側面及び前記第2の面、前記第2の半導体チップの側面及び前記第3の面に対向する面、及び前記接続部材を覆う封止樹脂とをさらに備えていることを特徴とする半導体装置。
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2013539505A JP6132769B2 (ja) | 2011-10-21 | 2012-09-05 | 半導体装置 |
Applications Claiming Priority (4)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2011232064 | 2011-10-21 | ||
JP2011232064 | 2011-10-21 | ||
PCT/JP2012/005629 WO2013057867A1 (ja) | 2011-10-21 | 2012-09-05 | 半導体装置 |
JP2013539505A JP6132769B2 (ja) | 2011-10-21 | 2012-09-05 | 半導体装置 |
Publications (2)
Publication Number | Publication Date |
---|---|
JPWO2013057867A1 true JPWO2013057867A1 (ja) | 2015-04-02 |
JP6132769B2 JP6132769B2 (ja) | 2017-05-24 |
Family
ID=48140538
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP2013539505A Active JP6132769B2 (ja) | 2011-10-21 | 2012-09-05 | 半導体装置 |
Country Status (4)
Country | Link |
---|---|
US (1) | US9117770B2 (ja) |
JP (1) | JP6132769B2 (ja) |
CN (1) | CN103620762B (ja) |
WO (1) | WO2013057867A1 (ja) |
Families Citing this family (19)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
WO2013051182A1 (ja) * | 2011-10-07 | 2013-04-11 | パナソニック株式会社 | 半導体装置及びその製造方法 |
US9287249B2 (en) * | 2012-04-11 | 2016-03-15 | Panasonic Intellectual Property Management Co., Ltd. | Semiconductor device |
KR102436789B1 (ko) | 2014-04-07 | 2022-08-26 | 니폰 덴키 가라스 가부시키가이샤 | 적층체, 반도체 패키지 제조 방법, 반도체 패키지 및 전자기기 |
JP2016122802A (ja) * | 2014-12-25 | 2016-07-07 | ルネサスエレクトロニクス株式会社 | 半導体装置 |
JPWO2016199437A1 (ja) * | 2015-06-12 | 2018-03-29 | 株式会社ソシオネクスト | 半導体装置 |
US10062648B2 (en) | 2016-02-26 | 2018-08-28 | Taiwan Semiconductor Manufacturing Company, Ltd. | Semiconductor package and method of forming the same |
TWI584425B (zh) * | 2016-06-27 | 2017-05-21 | 力成科技股份有限公司 | 扇出型晶圓級封裝結構 |
US9741690B1 (en) | 2016-09-09 | 2017-08-22 | Taiwan Semiconductor Manufacturing Company, Ltd. | Redistribution layers in semiconductor packages and methods of forming same |
US10304801B2 (en) * | 2016-10-31 | 2019-05-28 | Taiwan Semiconductor Manufacturing Company, Ltd. | Redistribution layers in semiconductor packages and methods of forming same |
US11158619B2 (en) | 2016-10-31 | 2021-10-26 | Taiwan Semiconductor Manufacturing Company, Ltd. | Redistribution layers in semiconductor packages and methods of forming same |
DE102017102534B4 (de) * | 2016-10-31 | 2022-01-13 | Taiwan Semiconductor Manufacturing Co. Ltd. | Umverteilungsschichten in Halbleiter-Packages und Verfahren zu deren Herstellung |
US10355371B2 (en) * | 2017-03-03 | 2019-07-16 | Microsoft Technology Licensing, Llc | Flexible conductive bonding |
US10461060B2 (en) * | 2017-05-31 | 2019-10-29 | Taiwan Semiconductor Manufacturing Co., Ltd. | Structure and formation method of chip package with redistribution layers |
US10181449B1 (en) * | 2017-09-28 | 2019-01-15 | Taiwan Semiconductor Manufacturing Co., Ltd. | Semiconductor structure |
JP2021040113A (ja) * | 2019-09-05 | 2021-03-11 | 株式会社デンソー | 半導体装置 |
CN110690188A (zh) * | 2019-10-15 | 2020-01-14 | 山东傲天环保科技有限公司 | 一种扇出型半导体封装结构 |
CN110739287B (zh) * | 2019-12-06 | 2021-06-15 | 江苏感测通电子科技有限公司 | 一种集成芯片封装结构 |
JP7413102B2 (ja) | 2020-03-17 | 2024-01-15 | キオクシア株式会社 | 半導体装置 |
JP2022083468A (ja) * | 2020-11-25 | 2022-06-06 | ソニーグループ株式会社 | 半導体装置 |
Citations (13)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2003179183A (ja) * | 1999-10-29 | 2003-06-27 | Hitachi Ltd | 半導体装置およびその製造方法 |
JP2003243604A (ja) * | 2002-02-13 | 2003-08-29 | Sony Corp | 電子部品及び電子部品の製造方法 |
JP2005251953A (ja) * | 2004-03-03 | 2005-09-15 | Nec Electronics Corp | 半導体装置 |
JP2005317585A (ja) * | 2004-04-27 | 2005-11-10 | Dainippon Printing Co Ltd | 電子部品内蔵モジュールおよびその製造方法 |
JP2007059950A (ja) * | 2006-12-04 | 2007-03-08 | Oki Electric Ind Co Ltd | 半導体装置内蔵基板及びその製造方法 |
WO2008056499A1 (en) * | 2006-11-06 | 2008-05-15 | Nec Corporation | Semiconductor device and method for manufacturing same |
JP2008193064A (ja) * | 2007-01-03 | 2008-08-21 | Advanced Chip Engineering Technology Inc | ダイ収容スルーホールを備えたウエハレベルパッケージおよびその方法 |
JP2008193121A (ja) * | 2008-04-24 | 2008-08-21 | Ibiden Co Ltd | 多層プリント配線板及び多層プリント配線板の製造方法 |
WO2009054414A1 (ja) * | 2007-10-22 | 2009-04-30 | Nec Corporation | 半導体装置 |
JP2009246404A (ja) * | 2009-07-30 | 2009-10-22 | Casio Comput Co Ltd | 半導体装置の製造方法 |
WO2011122228A1 (ja) * | 2010-03-31 | 2011-10-06 | 日本電気株式会社 | 半導体内蔵基板 |
WO2011125380A1 (ja) * | 2010-04-08 | 2011-10-13 | 日本電気株式会社 | 半導体素子内蔵配線基板 |
WO2012107972A1 (ja) * | 2011-02-10 | 2012-08-16 | パナソニック株式会社 | 半導体装置 |
Family Cites Families (18)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
EP0011418A1 (en) * | 1978-11-20 | 1980-05-28 | THE GENERAL ELECTRIC COMPANY, p.l.c. | Manufacture of electroluminescent display devices |
JPS62169458A (ja) * | 1986-01-22 | 1987-07-25 | Sumitomo Electric Ind Ltd | 半導体装置 |
JP3216622B2 (ja) | 1998-12-18 | 2001-10-09 | 日本電気株式会社 | 半導体装置 |
JP2002043762A (ja) * | 2000-07-27 | 2002-02-08 | Kyocera Corp | 多層配線基板 |
JP4347506B2 (ja) * | 2000-08-31 | 2009-10-21 | 株式会社ケーヒン | 半導体装置の実装構造 |
US7208344B2 (en) * | 2004-03-31 | 2007-04-24 | Aptos Corporation | Wafer level mounting frame for ball grid array packaging, and method of making and using the same |
JP2006253217A (ja) * | 2005-03-08 | 2006-09-21 | Sharp Corp | フレキシブル基板の接続構造、ピックアップ、電子機器およびフレキシブル基板の接続方法 |
JP4478049B2 (ja) * | 2005-03-15 | 2010-06-09 | 三菱電機株式会社 | 半導体装置 |
US7208345B2 (en) * | 2005-05-11 | 2007-04-24 | Infineon Technologies Ag | Method of manufacturing a semiconductor device comprising stacked chips and a corresponding semiconductor device |
EP2023701B1 (en) | 2006-05-29 | 2010-12-08 | Murata Manufacturing Co. Ltd. | Method for manufacturing ceramic multilayer substrate |
US8390107B2 (en) * | 2007-09-28 | 2013-03-05 | Intel Mobile Communications GmbH | Semiconductor device and methods of manufacturing semiconductor devices |
SG152086A1 (en) * | 2007-10-23 | 2009-05-29 | Micron Technology Inc | Packaged semiconductor assemblies and associated systems and methods |
JP5079456B2 (ja) * | 2007-11-06 | 2012-11-21 | 新光電気工業株式会社 | 半導体装置及びその製造方法 |
JP4405562B2 (ja) * | 2008-03-18 | 2010-01-27 | 株式会社東芝 | プリント配線板および電子機器 |
US8030136B2 (en) * | 2008-05-15 | 2011-10-04 | Stats Chippac, Ltd. | Semiconductor device and method of conforming conductive vias between insulating layers in saw streets |
US8093151B2 (en) * | 2009-03-13 | 2012-01-10 | Stats Chippac, Ltd. | Semiconductor die and method of forming noise absorbing regions between THVS in peripheral region of the die |
JP2011151104A (ja) * | 2010-01-20 | 2011-08-04 | Elpida Memory Inc | 半導体装置の製造方法及び半導体装置の中間構造体 |
US9666499B2 (en) * | 2012-10-31 | 2017-05-30 | Infineon Technologies Ag | Semiconductor device with encapsulant |
-
2012
- 2012-09-05 JP JP2013539505A patent/JP6132769B2/ja active Active
- 2012-09-05 CN CN201280030971.XA patent/CN103620762B/zh active Active
- 2012-09-05 WO PCT/JP2012/005629 patent/WO2013057867A1/ja active Application Filing
-
2014
- 2014-01-08 US US14/149,890 patent/US9117770B2/en active Active
Patent Citations (13)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2003179183A (ja) * | 1999-10-29 | 2003-06-27 | Hitachi Ltd | 半導体装置およびその製造方法 |
JP2003243604A (ja) * | 2002-02-13 | 2003-08-29 | Sony Corp | 電子部品及び電子部品の製造方法 |
JP2005251953A (ja) * | 2004-03-03 | 2005-09-15 | Nec Electronics Corp | 半導体装置 |
JP2005317585A (ja) * | 2004-04-27 | 2005-11-10 | Dainippon Printing Co Ltd | 電子部品内蔵モジュールおよびその製造方法 |
WO2008056499A1 (en) * | 2006-11-06 | 2008-05-15 | Nec Corporation | Semiconductor device and method for manufacturing same |
JP2007059950A (ja) * | 2006-12-04 | 2007-03-08 | Oki Electric Ind Co Ltd | 半導体装置内蔵基板及びその製造方法 |
JP2008193064A (ja) * | 2007-01-03 | 2008-08-21 | Advanced Chip Engineering Technology Inc | ダイ収容スルーホールを備えたウエハレベルパッケージおよびその方法 |
WO2009054414A1 (ja) * | 2007-10-22 | 2009-04-30 | Nec Corporation | 半導体装置 |
JP2008193121A (ja) * | 2008-04-24 | 2008-08-21 | Ibiden Co Ltd | 多層プリント配線板及び多層プリント配線板の製造方法 |
JP2009246404A (ja) * | 2009-07-30 | 2009-10-22 | Casio Comput Co Ltd | 半導体装置の製造方法 |
WO2011122228A1 (ja) * | 2010-03-31 | 2011-10-06 | 日本電気株式会社 | 半導体内蔵基板 |
WO2011125380A1 (ja) * | 2010-04-08 | 2011-10-13 | 日本電気株式会社 | 半導体素子内蔵配線基板 |
WO2012107972A1 (ja) * | 2011-02-10 | 2012-08-16 | パナソニック株式会社 | 半導体装置 |
Also Published As
Publication number | Publication date |
---|---|
CN103620762B (zh) | 2016-08-17 |
CN103620762A (zh) | 2014-03-05 |
US20140124941A1 (en) | 2014-05-08 |
JP6132769B2 (ja) | 2017-05-24 |
WO2013057867A1 (ja) | 2013-04-25 |
US9117770B2 (en) | 2015-08-25 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
JP6132769B2 (ja) | 半導体装置 | |
US11901332B2 (en) | Semiconductor device and manufacturing method thereof | |
US10109608B2 (en) | Semiconductor package | |
US10026707B2 (en) | Wafer level package and method | |
US20170250153A1 (en) | Electronic part, electronic device, and electronic apparatus | |
KR101333801B1 (ko) | 플립칩 기판 패키지 어셈블리 및 그 제조 프로세스 | |
KR101366455B1 (ko) | 반도체 장치, 패키징 방법 및 구조 | |
US10121736B2 (en) | Method of fabricating packaging layer of fan-out chip package | |
TW201933573A (zh) | 電子封裝件及其製法 | |
US20160049359A1 (en) | Interposer with conductive post and fabrication method thereof | |
TWI582919B (zh) | 無基板扇出型多晶片封裝構造及其製造方法 | |
US9899308B2 (en) | Semiconductor package and method of fabricating the same | |
JP2011166081A (ja) | 半導体装置、半導体パッケージ、インタポーザ、半導体装置の製造方法、及びインタポーザの製造方法 | |
US8098496B2 (en) | Wiring board for semiconductor device | |
US9355974B2 (en) | Semiconductor device and manufacturing method therefor | |
US20160079148A1 (en) | Substrate structure and method of manufacturing the same | |
TWI567843B (zh) | 封裝基板及其製法 | |
JP4728079B2 (ja) | 半導体装置用基板および半導体装置 | |
JP4737995B2 (ja) | 半導体装置 | |
KR20110076605A (ko) | 반도체 패키지 및 그 제조 방법 | |
US8603911B2 (en) | Semiconductor device and fabrication method thereof |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
A131 | Notification of reasons for refusal |
Free format text: JAPANESE INTERMEDIATE CODE: A131 Effective date: 20160308 |
|
A521 | Request for written amendment filed |
Free format text: JAPANESE INTERMEDIATE CODE: A523 Effective date: 20160421 |
|
A131 | Notification of reasons for refusal |
Free format text: JAPANESE INTERMEDIATE CODE: A131 Effective date: 20160913 |
|
A521 | Request for written amendment filed |
Free format text: JAPANESE INTERMEDIATE CODE: A523 Effective date: 20161108 |
|
TRDD | Decision of grant or rejection written | ||
A01 | Written decision to grant a patent or to grant a registration (utility model) |
Free format text: JAPANESE INTERMEDIATE CODE: A01 Effective date: 20170404 |
|
A61 | First payment of annual fees (during grant procedure) |
Free format text: JAPANESE INTERMEDIATE CODE: A61 Effective date: 20170418 |
|
R151 | Written notification of patent or utility model registration |
Ref document number: 6132769 Country of ref document: JP Free format text: JAPANESE INTERMEDIATE CODE: R151 |