JPWO2011078349A1 - 多数個取り配線基板および配線基板ならびに電子装置 - Google Patents
多数個取り配線基板および配線基板ならびに電子装置 Download PDFInfo
- Publication number
- JPWO2011078349A1 JPWO2011078349A1 JP2011547660A JP2011547660A JPWO2011078349A1 JP WO2011078349 A1 JPWO2011078349 A1 JP WO2011078349A1 JP 2011547660 A JP2011547660 A JP 2011547660A JP 2011547660 A JP2011547660 A JP 2011547660A JP WO2011078349 A1 JPWO2011078349 A1 JP WO2011078349A1
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- Prior art keywords
- main surface
- wiring board
- groove
- split groove
- electronic component
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- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/0011—Working of insulating substrates or insulating layers
- H05K3/0044—Mechanical working of the substrate, e.g. drilling or punching
- H05K3/0052—Depaneling, i.e. dividing a panel into circuit boards; Working of the edges of circuit boards
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
- H01L21/4803—Insulating or insulated parts, e.g. mountings, containers, diamond heatsinks
- H01L21/481—Insulating layers on insulating parts, with or without metallisation
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/12—Mountings, e.g. non-detachable insulating substrates
- H01L23/13—Mountings, e.g. non-detachable insulating substrates characterised by the shape
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
- H01L23/49827—Via connections through the substrates, e.g. pins going through the substrate, coaxial cables
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/93—Batch processes
- H01L24/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
- H01L24/96—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being encapsulated in a common layer, e.g. neo-wafer or pseudo-wafer, said common layer being separable into individual assemblies after connecting
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/02—Details
- H05K1/03—Use of materials for the substrate
- H05K1/0306—Inorganic insulating substrates, e.g. ceramic, glass
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/12—Passive devices, e.g. 2 terminal devices
- H01L2924/1204—Optical Diode
- H01L2924/12042—LASER
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/02—Details
- H05K1/0266—Marks, test patterns or identification means
- H05K1/0269—Marks, test patterns or identification means for visual or optical inspection
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
- H05K2201/09—Shape and layout
- H05K2201/09009—Substrate related
- H05K2201/0909—Preformed cutting or breaking line
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
- H05K2201/09—Shape and layout
- H05K2201/09145—Edge details
- H05K2201/09154—Bevelled, chamferred or tapered edge
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
- H05K2201/09—Shape and layout
- H05K2201/09818—Shape or layout details not covered by a single group of H05K2201/09009 - H05K2201/09809
- H05K2201/09918—Optically detected marks used for aligning tool relative to the PCB, e.g. for mounting of components
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2203/00—Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
- H05K2203/15—Position of the PCB during processing
- H05K2203/1572—Processing both sides of a PCB by the same process; Providing a similar arrangement of components on both sides; Making interlayer connections from two sides
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/0008—Apparatus or processes for manufacturing printed circuits for aligning or positioning of tools relative to the circuit board
Abstract
Description
1a・・・・配線基板領域
1b・・・・ダミー領域
1c・・・・切り欠き部
1d・・・・破断面
1e・・・・配線基板
2・・・・一方主面の分割溝
3・・・・他方主面の分割溝
4・・・・配線導体
5・・・・位置合わせ用のマーク
6・・・・凹部
7・・・・ダミー凹部
Claims (4)
- 中央部に電子部品搭載領域を有する複数の配線基板領域が縦横の並びに配置された母基板の両主面に、前記配線基板領域の境界に沿って分割溝が形成された多数個取り配線基板において、平面透視で、一方主面の分割溝と他方主面の分割溝とが縦方向または横方向のそれぞれで一方方向にずれて形成されており、前記一方主面の分割溝の底部と前記他方主面の分割溝の底部との間の距離が、前記一方主面の分割溝の底部と他方主面との間の距離および前記他方主面の分割溝の底部と一方主面との間の距離よりも小さいことを特徴とする多数個取り配線基板。
- 前記配線基板領域のそれぞれ1つの角部に位置合わせ用のマークが設けられていることを特徴とする請求項1記載の多数個取り配線基板。
- 平面視で矩形状の基板の隣り合う2つの側面に、主面に垂直な方向に対して傾いた破断面を有することを特徴とする配線基板。
- 請求項3に記載の配線基板に電子部品が搭載されていることを特徴とする電子装置。
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2011547660A JP5731404B2 (ja) | 2009-12-24 | 2010-12-24 | 多数個取り配線基板および配線基板ならびに電子装置 |
Applications Claiming Priority (6)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2009292013 | 2009-12-24 | ||
JP2009292013 | 2009-12-24 | ||
JP2010283289 | 2010-12-20 | ||
JP2010283289 | 2010-12-20 | ||
PCT/JP2010/073403 WO2011078349A1 (ja) | 2009-12-24 | 2010-12-24 | 多数個取り配線基板および配線基板ならびに電子装置 |
JP2011547660A JP5731404B2 (ja) | 2009-12-24 | 2010-12-24 | 多数個取り配線基板および配線基板ならびに電子装置 |
Publications (2)
Publication Number | Publication Date |
---|---|
JPWO2011078349A1 true JPWO2011078349A1 (ja) | 2013-05-09 |
JP5731404B2 JP5731404B2 (ja) | 2015-06-10 |
Family
ID=44195874
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP2011547660A Active JP5731404B2 (ja) | 2009-12-24 | 2010-12-24 | 多数個取り配線基板および配線基板ならびに電子装置 |
Country Status (5)
Country | Link |
---|---|
US (1) | US8975535B2 (ja) |
EP (1) | EP2519085B1 (ja) |
JP (1) | JP5731404B2 (ja) |
CN (1) | CN102484943B (ja) |
WO (1) | WO2011078349A1 (ja) |
Families Citing this family (9)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
KR101548816B1 (ko) * | 2013-11-11 | 2015-08-31 | 삼성전기주식회사 | 인쇄회로기판 및 그 제조방법 |
JP6276040B2 (ja) * | 2014-01-20 | 2018-02-07 | 日本特殊陶業株式会社 | 部品搭載用パッケージの製造方法 |
WO2015182229A1 (ja) * | 2014-05-27 | 2015-12-03 | 株式会社村田製作所 | マザーセラミック基板、セラミック基板、マザーモジュール部品、モジュール部品およびマザーセラミック基板の製造方法 |
KR101650076B1 (ko) * | 2014-06-10 | 2016-08-22 | 한국미쯔보시다이아몬드공업(주) | 취성 재료 기판의 가공방법 |
KR102521372B1 (ko) * | 2016-02-12 | 2023-04-14 | 삼성전자주식회사 | 마크 위치 예측 방법 |
CN108781502B (zh) | 2016-04-22 | 2021-11-30 | 京瓷株式会社 | 多连片布线基板、布线基板 |
CN111684673B (zh) * | 2018-02-16 | 2023-04-18 | 京瓷株式会社 | 多连片式元件收纳用封装件以及多连片式光半导体装置 |
WO2019240000A1 (ja) * | 2018-06-11 | 2019-12-19 | 株式会社村田製作所 | 電気素子の製造方法、電気素子、および電気素子の実装構造 |
WO2020203738A1 (ja) * | 2019-03-29 | 2020-10-08 | 株式会社オートネットワーク技術研究所 | 配線モジュール |
Family Cites Families (14)
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JPS5497766U (ja) * | 1977-12-21 | 1979-07-10 | ||
JP3395620B2 (ja) | 1997-12-16 | 2003-04-14 | 日亜化学工業株式会社 | 半導体発光素子及びその製造方法 |
JPH11346038A (ja) * | 1998-06-01 | 1999-12-14 | Mitsubishi Plastics Ind Ltd | 溝付き金属ベース回路基板 |
TW562737B (en) * | 2000-11-27 | 2003-11-21 | Murata Manufacturing Co | Method of manufacturing ceramic multi-layer substrate, and unbaked composite laminated body |
US7250352B2 (en) * | 2002-04-24 | 2007-07-31 | Sanyo Electric Co., Ltd. | Methods for manufacturing a hybrid integrated circuit device |
JP2004200615A (ja) | 2002-12-20 | 2004-07-15 | Kyocera Corp | 多数個取り配線基板 |
JP4186746B2 (ja) * | 2003-08-04 | 2008-11-26 | 松下電器産業株式会社 | セラミック基板とその製造方法 |
US7232957B2 (en) * | 2003-09-25 | 2007-06-19 | Sanyo Electric Co., Ltd. | Hybrid integrated circuit device and method of manufacturing the same |
JP2005136129A (ja) * | 2003-10-30 | 2005-05-26 | Kyocera Corp | 多数個取り配線基板 |
JP4488733B2 (ja) * | 2003-12-24 | 2010-06-23 | 三洋電機株式会社 | 回路基板の製造方法および混成集積回路装置の製造方法。 |
JP4511311B2 (ja) * | 2004-10-28 | 2010-07-28 | 京セラ株式会社 | 多数個取り配線基板および電子装置 |
JP4929893B2 (ja) * | 2006-07-20 | 2012-05-09 | 株式会社デンソー | セラミック基板の製造方法 |
JP5108496B2 (ja) * | 2007-12-26 | 2012-12-26 | 三洋電機株式会社 | 回路基板およびその製造方法、回路装置およびその製造方法 |
CN101488486B (zh) * | 2008-01-15 | 2010-06-02 | 力成科技股份有限公司 | 可开槽式线路基板 |
-
2010
- 2010-12-24 WO PCT/JP2010/073403 patent/WO2011078349A1/ja active Application Filing
- 2010-12-24 EP EP10839578.1A patent/EP2519085B1/en active Active
- 2010-12-24 US US13/393,447 patent/US8975535B2/en active Active
- 2010-12-24 JP JP2011547660A patent/JP5731404B2/ja active Active
- 2010-12-24 CN CN201080038696.7A patent/CN102484943B/zh active Active
Also Published As
Publication number | Publication date |
---|---|
CN102484943A (zh) | 2012-05-30 |
US8975535B2 (en) | 2015-03-10 |
EP2519085B1 (en) | 2019-02-27 |
WO2011078349A1 (ja) | 2011-06-30 |
CN102484943B (zh) | 2016-03-16 |
EP2519085A4 (en) | 2013-05-08 |
EP2519085A1 (en) | 2012-10-31 |
JP5731404B2 (ja) | 2015-06-10 |
US20120222895A1 (en) | 2012-09-06 |
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