JP5355246B2 - 多数個取り配線基板および配線基板ならびに電子装置 - Google Patents
多数個取り配線基板および配線基板ならびに電子装置 Download PDFInfo
- Publication number
- JP5355246B2 JP5355246B2 JP2009150614A JP2009150614A JP5355246B2 JP 5355246 B2 JP5355246 B2 JP 5355246B2 JP 2009150614 A JP2009150614 A JP 2009150614A JP 2009150614 A JP2009150614 A JP 2009150614A JP 5355246 B2 JP5355246 B2 JP 5355246B2
- Authority
- JP
- Japan
- Prior art keywords
- wiring board
- groove
- electronic component
- region
- dividing
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
Images
Classifications
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/0011—Working of insulating substrates or insulating layers
- H05K3/0044—Mechanical working of the substrate, e.g. drilling or punching
- H05K3/0052—Depaneling, i.e. dividing a panel into circuit boards; Working of the edges of circuit boards
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/02—Containers; Seals
- H01L23/04—Containers; Seals characterised by the shape of the container or parts, e.g. caps, walls
- H01L23/053—Containers; Seals characterised by the shape of the container or parts, e.g. caps, walls the container being a hollow construction and having an insulating or insulated base as a mounting for the semiconductor body
- H01L23/055—Containers; Seals characterised by the shape of the container or parts, e.g. caps, walls the container being a hollow construction and having an insulating or insulated base as a mounting for the semiconductor body the leads having a passage through the base
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/12—Mountings, e.g. non-detachable insulating substrates
- H01L23/13—Mountings, e.g. non-detachable insulating substrates characterised by the shape
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/93—Batch processes
- H01L24/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
- H01L24/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/93—Batch processes
- H01L2224/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
- H01L2224/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
- H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
- H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
- H01L23/3121—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/095—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00 with a principal constituent of the material being a combination of two or more materials provided in the groups H01L2924/013 - H01L2924/0715
- H01L2924/097—Glass-ceramics, e.g. devitrified glass
- H01L2924/09701—Low temperature co-fired ceramic [LTCC]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/12—Passive devices, e.g. 2 terminal devices
- H01L2924/1204—Optical Diode
- H01L2924/12042—LASER
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/14—Integrated circuits
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/1515—Shape
- H01L2924/15158—Shape the die mounting substrate being other than a cuboid
- H01L2924/15159—Side view
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/153—Connection portion
- H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/161—Cap
- H01L2924/1615—Shape
- H01L2924/16152—Cap comprising a cavity for hosting the device, e.g. U-shaped cap
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/161—Cap
- H01L2924/162—Disposition
- H01L2924/16251—Connecting to an item not being a semiconductor or solid-state body, e.g. cap-to-substrate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/161—Cap
- H01L2924/163—Connection portion, e.g. seal
- H01L2924/16315—Shape
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
- H01L2924/1901—Structure
- H01L2924/1904—Component type
- H01L2924/19041—Component type being a capacitor
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
- H01L2924/1901—Structure
- H01L2924/1904—Component type
- H01L2924/19043—Component type being a resistor
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
- H01L2924/191—Disposition
- H01L2924/19101—Disposition of discrete passive components
- H01L2924/19102—Disposition of discrete passive components in a stacked assembly with the semiconductor or solid state device
- H01L2924/19103—Disposition of discrete passive components in a stacked assembly with the semiconductor or solid state device interposed between the semiconductor or solid-state device and the die mounting substrate, i.e. chip-on-passive
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/30—Technical effects
- H01L2924/301—Electrical effects
- H01L2924/3025—Electromagnetic shielding
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/30—Technical effects
- H01L2924/35—Mechanical effects
- H01L2924/351—Thermal stress
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
- H05K2201/09—Shape and layout
- H05K2201/09009—Substrate related
- H05K2201/09036—Recesses or grooves in insulating substrate
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
- H05K2201/09—Shape and layout
- H05K2201/09009—Substrate related
- H05K2201/0909—Preformed cutting or breaking line
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
- H05K2201/10—Details of components or other objects attached to or integrated in a printed circuit board
- H05K2201/10227—Other objects, e.g. metallic pieces
- H05K2201/10371—Shields or metal cases
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2203/00—Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
- H05K2203/01—Tools for processing; Objects used during processing
- H05K2203/0195—Tool for a process not provided for in H05K3/00, e.g. tool for handling objects using suction, for deforming objects, for applying local pressure
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2203/00—Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
- H05K2203/02—Details related to mechanical or acoustic processing, e.g. drilling, punching, cutting, using ultrasound
- H05K2203/0228—Cutting, sawing, milling or shearing
Description
1a・・・配線基板領域
1b・・・電子部品搭載領域
1c・・・蓋体を接合する領域
1d・・・第2の電子部品搭載領域
1e・・・配線基板
2(2x,2y)・・・・分割溝
2a(2ya)・・・・第2の分割溝
3(3x,3y)・・・溝
4・・・配線導体
5・・・・凹部
6,7・・・カッター刃
8・・・・電子部品
9・・・・蓋体
10・・・・封止材
11・・・・接合材
12・・・・第2の電子部品
Claims (4)
- 中央部に電子部品搭載領域を有する複数の配線基板領域が縦横の並びに配置された母基板の一方主面に、前記配線基板領域の境界に分割溝が形成された多数個取り配線基板において、前記母基板の一方主面の前記電子部品搭載領域と前記分割溝との間に蓋体を接合する領域があり、この蓋体を接合する領域内に、この領域の幅以下で前記分割溝の深さよりも浅い溝を備えており、該溝は、隣接する前記配線基板領域で前記分割溝に沿って連続していることを特徴とする多数個取り配線基板。
- 請求項1に記載の多数個取り配線基板が前記分割溝に沿って分割されたものであることを特徴とする配線基板。
- 請求項1に記載の多数個取り配線基板が前記分割溝に沿って分割されたものであって、一方主面に、前記電子部品搭載領域と、該電子部品搭載領域と外縁との間に位置して両端が対向する側面に至る前記溝とを有することを特徴とする配線基板。
- 請求項2または請求項3に記載の配線基板の前記電子部品搭載領域に電子部品が搭載され、該電子部品を覆うように前記蓋体が接合されていることを特徴とする電子装置。
Priority Applications (5)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2009150614A JP5355246B2 (ja) | 2009-06-25 | 2009-06-25 | 多数個取り配線基板および配線基板ならびに電子装置 |
EP10792138.9A EP2448377B1 (en) | 2009-06-25 | 2010-06-23 | Multi-pattern wiring substrate and electronic device |
US13/254,138 US8658908B2 (en) | 2009-06-25 | 2010-06-23 | Multiple patterning wiring board, wiring board and electronic apparatus |
CN201080009867.3A CN102342185B (zh) | 2009-06-25 | 2010-06-23 | 多个组合式布线基板、布线基板和电子装置 |
PCT/JP2010/060658 WO2010150820A1 (ja) | 2009-06-25 | 2010-06-23 | 多数個取り配線基板および配線基板ならびに電子装置 |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2009150614A JP5355246B2 (ja) | 2009-06-25 | 2009-06-25 | 多数個取り配線基板および配線基板ならびに電子装置 |
Publications (2)
Publication Number | Publication Date |
---|---|
JP2011009400A JP2011009400A (ja) | 2011-01-13 |
JP5355246B2 true JP5355246B2 (ja) | 2013-11-27 |
Family
ID=43386589
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP2009150614A Expired - Fee Related JP5355246B2 (ja) | 2009-06-25 | 2009-06-25 | 多数個取り配線基板および配線基板ならびに電子装置 |
Country Status (5)
Country | Link |
---|---|
US (1) | US8658908B2 (ja) |
EP (1) | EP2448377B1 (ja) |
JP (1) | JP5355246B2 (ja) |
CN (1) | CN102342185B (ja) |
WO (1) | WO2010150820A1 (ja) |
Families Citing this family (18)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
WO2012108229A1 (ja) * | 2011-02-07 | 2012-08-16 | 株式会社村田製作所 | セラミック基板およびその製造方法 |
JP5763962B2 (ja) | 2011-04-19 | 2015-08-12 | 日本特殊陶業株式会社 | セラミック配線基板、多数個取りセラミック配線基板、およびその製造方法 |
JP5945099B2 (ja) * | 2011-04-20 | 2016-07-05 | 日本特殊陶業株式会社 | 配線基板、多数個取り配線基板、およびその製造方法 |
JP6006474B2 (ja) | 2011-04-25 | 2016-10-12 | 日本特殊陶業株式会社 | 配線基板、多数個取り配線基板、およびその製造方法 |
JPWO2013099854A1 (ja) * | 2011-12-27 | 2015-05-07 | 日本特殊陶業株式会社 | 配線基板および多数個取り配線基板 |
KR20130081515A (ko) * | 2012-01-09 | 2013-07-17 | 삼성전자주식회사 | Led 패키지용 기판 및 led 패키지 제조방법 |
JP6129491B2 (ja) * | 2012-08-06 | 2017-05-17 | Ngkエレクトロデバイス株式会社 | 多数個取り配線基板 |
JP6029173B2 (ja) * | 2013-02-04 | 2016-11-24 | Ngkエレクトロデバイス株式会社 | セラミックパッケージ及びその製造方法 |
US9704791B2 (en) * | 2013-10-23 | 2017-07-11 | Kyocera Corporation | Wiring board and electronic device |
US9820384B2 (en) * | 2013-12-11 | 2017-11-14 | Intel Corporation | Flexible electronic assembly method |
JP6403092B2 (ja) * | 2014-10-20 | 2018-10-10 | 日立金属株式会社 | セラミック基板およびそれを用いた電子部品の製造方法 |
WO2017183688A1 (ja) | 2016-04-22 | 2017-10-26 | 京セラ株式会社 | 多数個取り配線基板、配線基板および多数個取り配線基板の製造方法 |
JP6844687B2 (ja) * | 2017-12-08 | 2021-03-17 | 東洋紡株式会社 | ポリエステルエラストマー樹脂組成物 |
US11490511B2 (en) | 2018-06-28 | 2022-11-01 | Kyocera Corporation | Circuit board and electronic device that includes it |
JP6550516B1 (ja) * | 2018-09-18 | 2019-07-24 | レノボ・シンガポール・プライベート・リミテッド | パネル、pcbおよびpcbの製造方法 |
DE102018128570A1 (de) * | 2018-11-14 | 2020-05-14 | Osram Opto Semiconductors Gmbh | Verfahren zur herstellung einer vielzahl strahlungsemittierender bauelemente, strahlungsemittierendes bauelement, verfahren zur herstellung eines verbindungsträgers und verbindungsträger |
JP7200705B2 (ja) | 2019-01-31 | 2023-01-10 | セイコーエプソン株式会社 | 振動デバイス、振動デバイスの製造方法、振動モジュール、電子機器および移動体 |
JP7135947B2 (ja) * | 2019-03-12 | 2022-09-13 | 三菱マテリアル株式会社 | 絶縁回路基板の製造方法及びセラミックス板 |
Family Cites Families (16)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US3608186A (en) * | 1969-10-30 | 1971-09-28 | Jearld L Hutson | Semiconductor device manufacture with junction passivation |
JPH0750700B2 (ja) * | 1989-06-27 | 1995-05-31 | 三菱電機株式会社 | 半導体チップの製造方法 |
US5124677A (en) * | 1990-08-22 | 1992-06-23 | Harris Corporation | Waffleline-configured surface-mount package for high frequency signal coupling applications |
JPH10270813A (ja) * | 1997-03-27 | 1998-10-09 | Murata Mfg Co Ltd | ブレーク溝付きセラミック基板およびこのセラミック基板から製造される電子部品 |
US6603193B2 (en) * | 2001-09-06 | 2003-08-05 | Silicon Bandwidth Inc. | Semiconductor package |
TW551611U (en) * | 2002-12-13 | 2003-09-01 | Kingpak Tech Inc | Improved structure of photo sensor package |
JP2005033450A (ja) * | 2003-07-11 | 2005-02-03 | Murata Mfg Co Ltd | 電子部品およびその製造方法 |
JP2005064230A (ja) * | 2003-08-12 | 2005-03-10 | Disco Abrasive Syst Ltd | 板状物の分割方法 |
JP2006041456A (ja) | 2004-06-25 | 2006-02-09 | Kyocera Corp | 光半導体素子収納用パッケージおよび光半導体装置 |
JP4511311B2 (ja) * | 2004-10-28 | 2010-07-28 | 京セラ株式会社 | 多数個取り配線基板および電子装置 |
US7492044B2 (en) * | 2005-10-06 | 2009-02-17 | Lenovo (Singapore) Pte. Ltd. | System and method for decreasing stress on solder holding BGA module to computer motherboard |
JP5373262B2 (ja) * | 2006-12-06 | 2013-12-18 | 株式会社デンソー | 半導体基板のキャップ固着方法 |
US20080192446A1 (en) * | 2007-02-09 | 2008-08-14 | Johannes Hankofer | Protection For Circuit Boards |
JP2009105212A (ja) * | 2007-10-23 | 2009-05-14 | Toshiba Corp | プリント配線板および電子機器 |
US7906371B2 (en) * | 2008-05-28 | 2011-03-15 | Stats Chippac, Ltd. | Semiconductor device and method of forming holes in substrate to interconnect top shield and ground shield |
JP5052470B2 (ja) | 2008-09-25 | 2012-10-17 | 京セラ株式会社 | 多数個取り配線基板および配線基板ならびに電子装置 |
-
2009
- 2009-06-25 JP JP2009150614A patent/JP5355246B2/ja not_active Expired - Fee Related
-
2010
- 2010-06-23 CN CN201080009867.3A patent/CN102342185B/zh not_active Expired - Fee Related
- 2010-06-23 US US13/254,138 patent/US8658908B2/en not_active Expired - Fee Related
- 2010-06-23 EP EP10792138.9A patent/EP2448377B1/en not_active Not-in-force
- 2010-06-23 WO PCT/JP2010/060658 patent/WO2010150820A1/ja active Application Filing
Also Published As
Publication number | Publication date |
---|---|
CN102342185A (zh) | 2012-02-01 |
EP2448377A4 (en) | 2014-03-12 |
EP2448377B1 (en) | 2015-11-25 |
JP2011009400A (ja) | 2011-01-13 |
US8658908B2 (en) | 2014-02-25 |
EP2448377A1 (en) | 2012-05-02 |
US20110315439A1 (en) | 2011-12-29 |
CN102342185B (zh) | 2015-04-22 |
WO2010150820A1 (ja) | 2010-12-29 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
JP5355246B2 (ja) | 多数個取り配線基板および配線基板ならびに電子装置 | |
JP5731404B2 (ja) | 多数個取り配線基板および配線基板ならびに電子装置 | |
JP5823043B2 (ja) | 電子素子搭載用基板、電子装置および撮像モジュール | |
JP5964858B2 (ja) | 撮像素子収納用パッケージおよび撮像装置 | |
JP6042885B2 (ja) | 電子素子搭載用基板および電子装置 | |
CN107785327B (zh) | 电子部件搭载用基板、电子装置以及电子模块 | |
JP5052470B2 (ja) | 多数個取り配線基板および配線基板ならびに電子装置 | |
JP2018032704A (ja) | 電子素子実装用基板、電子装置および電子モジュール | |
JP5052398B2 (ja) | 多数個取り配線基板および配線基板ならびに電子装置 | |
EP2637484B1 (en) | Multi-part wired substrate, wired substrate, and electronic device | |
JP5312250B2 (ja) | 電子部品収納用パッケージおよび電子装置 | |
JP2011049354A (ja) | 電子装置 | |
JP5247415B2 (ja) | 多数個取り配線基板および配線基板ならびに電子装置 | |
CN107615477B (zh) | 电子元件安装用基板以及电子装置 | |
CN114762098A (zh) | 电子部件收纳用封装件、电子装置及电子模块 | |
JP4812516B2 (ja) | 複数個取り配線基板 | |
JP5574848B2 (ja) | 多数個取り配線基板 | |
JP5460002B2 (ja) | 多数個取り配線基板および配線基板ならびに電子装置 | |
JP6258768B2 (ja) | 配線基板および電子装置 | |
JP2012191054A (ja) | 多数個取り配線基板および配線基板 | |
JP2008211017A (ja) | 台座付母基板および電子部品実装母基板の製造方法、ならびに電子装置 |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
A621 | Written request for application examination |
Free format text: JAPANESE INTERMEDIATE CODE: A621 Effective date: 20111115 |
|
A131 | Notification of reasons for refusal |
Free format text: JAPANESE INTERMEDIATE CODE: A131 Effective date: 20130108 |
|
A521 | Written amendment |
Free format text: JAPANESE INTERMEDIATE CODE: A523 Effective date: 20130301 |
|
TRDD | Decision of grant or rejection written | ||
A01 | Written decision to grant a patent or to grant a registration (utility model) |
Free format text: JAPANESE INTERMEDIATE CODE: A01 Effective date: 20130730 |
|
A61 | First payment of annual fees (during grant procedure) |
Free format text: JAPANESE INTERMEDIATE CODE: A61 Effective date: 20130827 |
|
R150 | Certificate of patent or registration of utility model |
Ref document number: 5355246 Country of ref document: JP Free format text: JAPANESE INTERMEDIATE CODE: R150 Free format text: JAPANESE INTERMEDIATE CODE: R150 |
|
LAPS | Cancellation because of no payment of annual fees |