CN107785327B - 电子部件搭载用基板、电子装置以及电子模块 - Google Patents

电子部件搭载用基板、电子装置以及电子模块 Download PDF

Info

Publication number
CN107785327B
CN107785327B CN201710716548.XA CN201710716548A CN107785327B CN 107785327 B CN107785327 B CN 107785327B CN 201710716548 A CN201710716548 A CN 201710716548A CN 107785327 B CN107785327 B CN 107785327B
Authority
CN
China
Prior art keywords
electronic component
electrode
insulating base
component mounting
substrate
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Active
Application number
CN201710716548.XA
Other languages
English (en)
Other versions
CN107785327A (zh
Inventor
村上健策
森山阳介
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Kyocera Corp
Original Assignee
Kyocera Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Kyocera Corp filed Critical Kyocera Corp
Publication of CN107785327A publication Critical patent/CN107785327A/zh
Application granted granted Critical
Publication of CN107785327B publication Critical patent/CN107785327B/zh
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49838—Geometry or layout
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/12—Mountings, e.g. non-detachable insulating substrates
    • H01L23/13—Mountings, e.g. non-detachable insulating substrates characterised by the shape
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/02—Containers; Seals
    • H01L23/04—Containers; Seals characterised by the shape of the container or parts, e.g. caps, walls
    • H01L23/053—Containers; Seals characterised by the shape of the container or parts, e.g. caps, walls the container being a hollow construction and having an insulating or insulated base as a mounting for the semiconductor body
    • H01L23/057—Containers; Seals characterised by the shape of the container or parts, e.g. caps, walls the container being a hollow construction and having an insulating or insulated base as a mounting for the semiconductor body the leads being parallel to the base
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/12—Mountings, e.g. non-detachable insulating substrates
    • H01L23/14—Mountings, e.g. non-detachable insulating substrates characterised by the material or its electrical properties
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/492—Bases or plates or solder therefor
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49827—Via connections through the substrates, e.g. pins going through the substrate, coaxial cables
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13099—Material
    • H01L2224/131—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/13101—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of less than 400°C
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13099—Material
    • H01L2224/131—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/13138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/13144—Gold [Au] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13099—Material
    • H01L2224/13198—Material with a principal constituent of the material being a combination of two or more materials in the form of a matrix with a filler, i.e. being a hybrid material, e.g. segmented structures, foams
    • H01L2224/13199—Material of the matrix
    • H01L2224/1329—Material of the matrix with a principal constituent of the material being a polymer, e.g. polyester, phenolic based polymer, epoxy
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/16227—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation the bump connector connecting to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48105—Connecting bonding areas at different heights
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49805—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers the leads being also applied on the sidewalls or the bottom of the substrate, e.g. leadless packages for surface mounting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49822—Multilayer substrates
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L24/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L24/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42—Wire connectors; Manufacturing methods related thereto
    • H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L24/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/12—Passive devices, e.g. 2 terminal devices
    • H01L2924/1204—Optical Diode
    • H01L2924/12041—LED
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/12—Passive devices, e.g. 2 terminal devices
    • H01L2924/1204—Optical Diode
    • H01L2924/12043—Photo diode
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/14—Integrated circuits
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/1515—Shape
    • H01L2924/15153—Shape the die mounting substrate comprising a recess for hosting the device
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/1517—Multilayer substrate
    • H01L2924/15192—Resurf arrangement of the internal vias
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1532—Connection portion the connection portion being formed on the die mounting surface of the substrate
    • H01L2924/15323—Connection portion the connection portion being formed on the die mounting surface of the substrate being a land array, e.g. LGA
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/161—Cap
    • H01L2924/1615—Shape
    • H01L2924/16195—Flat cap [not enclosing an internal cavity]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/161—Cap
    • H01L2924/162—Disposition
    • H01L2924/16251—Connecting to an item not being a semiconductor or solid-state body, e.g. cap-to-substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/161—Cap
    • H01L2924/163—Connection portion, e.g. seal
    • H01L2924/1631—Structure

Landscapes

  • Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Geometry (AREA)
  • Structures For Mounting Electric Components On Printed Circuit Boards (AREA)
  • Structure Of Printed Boards (AREA)
  • Cooling Or The Like Of Semiconductors Or Solid State Devices (AREA)
  • Printing Elements For Providing Electric Connections Between Printed Circuits (AREA)

Abstract

电子部件搭载用基板(1)具有：在俯视下呈矩形形状的绝缘基体(11)，其具有第一主面(11a)以及与第一主面(11a)相对的第二主面(11b)，绝缘基体(11)在第一主面(11a)开口，且具有凹入部(12)；带状的金属层(13)，其设置于凹入部(12)的侧壁上；以及电极(14)，其从凹入部(12)的底面到绝缘基体(11)的内部地设置，电极(14)的端部(14a)设置于绝缘基体(11)的内部，端部(14a)具有向第二主面(11b)侧倾斜的倾斜部。

Description

电子部件搭载用基板、电子装置以及电子模块
技术领域
本发明涉及电子部件搭载用基板、电子装置以及电子模块。
背景技术
以往，已知在绝缘基体的主面搭载电子部件的电子部件搭载用基板以及电子装置(例如参照专利文献1)。
在这样的电子部件搭载用基板中，绝缘基体具有凹入部和设置于凹入部的底面的电极。
在先技术文献
专利文献
专利文献1：日本特开2006-049551号公报
发明要解决的课题
然而，近年来，电子装置逐渐高功能化以及小型化，在凹入部的底面设置的电极的大小也变小。若为了提高电极与绝缘基体的接合强度而使电极的端部延伸至绝缘基体内，则容易在例如构成电极周围的绝缘基体的绝缘层之间设置有空隙，担心凹入部的侧壁的气密性会降低。
发明内容
用于解决课题的方案
根据本发明的一个方案，电子部件搭载用基板具备：在俯视下呈矩形形状的绝缘基体，其具有第一主面以及与该第一主面相对的第二主面，所述绝缘基体在所述第一主面开口，且具有凹入部；带状的金属层，其设置于所述凹入部的侧壁上；以及电极，其从所述凹入部的底面到所述绝缘基体的内部地设置，该电极的端部设置于所述绝缘基体的内部，所述端部具有向所述第二主面侧倾斜的倾斜部。
根据本发明的一个方案，电子装置具有上述结构的电子部件搭载用基板和搭载于该电子部件搭载用基板的电子部件。
根据本发明的一个方案，电子模块具有：模块用基板，其具有连接焊盘；以及上述结构的电子装置，其经由焊料而与连接焊盘连接。
发明效果
在本发明的一方案的电子部件搭载用基板中，具有：在俯视下呈矩形形状的绝缘基体，其具有第一主面以及与第一主面相对的第二主面，该绝缘基体在第一主面开口，且具有凹入部；带状的金属层，其设置于凹入部的侧壁上；以及电极，其从凹入部的底面到绝缘基体的内部地设置，电极的端部设置于绝缘基体的内部，端部具有向第二主面侧倾斜的倾斜部。根据上述结构，能够形成如下的电子部件搭载用基板：通过在电极的端部设置倾斜部而使电极的厚度薄，并将其埋设于绝缘基体的第二主面侧，由此能够抑制在例如构成电极周围的绝缘基体的绝缘层之间设置有空隙的情况，抑制绝缘基体的内部的电极周围处的气密性降低，抑制凹入部周围的气密性降低。
在本发明的一个方案的电子装置中，通过具有上述结构的电子部件搭载用基板和搭载于电子部件搭载用基板的电子部件，能够形成长期可靠性优异的电子装置。
在本发明的一方案的电子模块中，通过包括具有连接焊盘的模块用基板和经由焊料而与连接焊盘连接的上述结构的电子装置，能够形成长期可靠性优异的电子模块。
附图说明
图1的(a)是表示本发明的第一实施方式的电子装置的俯视图，(b)是(a)的仰视图。
图2是表示图1中的电子部件搭载用基板的电极的内部俯视图。
图3的(a)是图1的(a)所示的电子装置的A-A线处的纵剖视图，(b)是图1的(a)所示的电子装置的B-B线处的纵剖视图，(c)是(a)的C部处的主要部分放大纵剖视图。
图4是表示将图1中的电子装置安装于模块用基板所得的电子模块的纵剖视图。
图5的(a)是表示本发明的第二实施方式的电子装置的俯视图，(b)是(a)的仰视图。
图6是表示图5中的电子部件搭载用基板的电极的内部俯视图。
图7的(a)是图5的(a)所示的电子装置的A-A线处的纵剖视图，(b)是(a)的C部处的主要部分放大纵剖视图。
图8的(a)是表示本发明的第一实施方式的电子装置的另一例的俯视图，(b)是(a)的仰视图。
图9的(a)是表示本发明的第一实施方式的电子装置的另一例的俯视图，(b)是(a)的仰视图。
图10的(a)是图9的(a)所示的电子装置的A-A线处的纵剖视图，(b)是(a)的C部处的主要部分放大纵剖视图。
附图文字说明
1····电子部件搭载用基板
11····绝缘基体
11a···第一主面
11b···第二主面
11c···绝缘层
12····凹入部
13····金属层
14····电极
14a···端部
14b···倾斜部
15····布线导体
16····腔室
2····电子部件
3····连接构件
4····盖体
5····模块用基板
51····连接焊盘
6····焊料
具体实施方式
参照附图来说明本发明的几个例示的实施方式。
(第一实施方式)
如图1～图4所示，本发明的第一实施方式的电子装置包括电子部件搭载用基板1和搭载于电子部件搭载用基板1的电子部件2。如图4所示，电子装置使用焊料6而连接于例如构成电子模块的模块用基板5上。
本实施方式的电子部件搭载用基板1具有：在俯视下呈矩形形状的绝缘基体11，其具有第一主面11a以及与第一主面11a相对的第二主面11b，该绝缘基体11在第一主面11a开口，具有凹入部12；带状的金属层13，其设置于凹入部12的侧壁上；以及电极14，其从凹入部12的底面到绝缘基体11的内部地设置。布线导体15设置于绝缘基体11的表面以及内部。另外，绝缘基体11具有在第一主面11a开口而得到的腔室16。电极14的端部14a设置于绝缘基体11的内部。电极14的端部14a具有向第二主面11b侧倾斜的倾斜部14b。在图1～图4中，上方向是指假想的z轴的正向。需要说明的是，以下的说明中的上下的区别是为了方便说明，实际上并不限定使用电子部件搭载用基板1等时的上下。
在图1～图3所示的例子中，第一实施方式的电子部件搭载用基板1具有：两个凹入部12，其在绝缘基体11的第一主面11a以及侧面开口；和一个腔室16，其设置于两个凹入部12之间，在第一主面11a开口。在图1～图3所示的例子中，第一实施方式的电子部件搭载用基板1中的绝缘基体11由四层绝缘层11c形成，凹入部12设置于第一主面11a侧的第一个绝缘层，腔室16设置于第一主面11a侧的第一个～第三个绝缘层11c。电极14设置于第一主面11a侧的第二个绝缘层11c的表面、即凹入部12的底面。
在图2所示的例子中，将在俯视透视下与凹入部12的内壁面重叠的区域用虚线示出。另外，在图2所示的例子中，将在俯视透视下与布线导体15的贯通导体的侧面重叠的区域用虚线示出。另外，在图2所示的例子中，将在俯视透视下与金属层13的内缘部及外缘部重叠的区域用虚线示出。在图2所示的例子中，在俯视透视下，两个电极14的端部14a分别与金属层13重叠。
绝缘基体11具有第一主面11a(在图1～图4中为上表面)以及第二主面11b(在图1～图4中为下表面)、以及侧面。绝缘基体11由多个绝缘层11c构成，具有在第一主面11a开口而且在绝缘基体11的侧面开口的凹入部12。在凹入部12的底面设置有电极14，该电极14用于与模块用基板5的连接焊盘51连接。绝缘基体11在俯视下、即从与主面垂直的方向观察时具有矩形的板状的形状。另外，绝缘基体11具有在第一主面11a开口且与凹入部12相邻的腔室16。绝缘基体11作为用于支承电子部件2的支承体而发挥功能，电子部件2经由焊料凸点、金属凸点或导电性树脂(各向异性导电树脂等)等连接构件3而粘接固定在腔室16的底面上。
绝缘基体11例如可以使用氧化铝质烧结体(氧化铝陶瓷)，氮化铝质烧结体，氮化硅质烧结体、莫来石质烧结体或玻璃陶瓷烧结体等陶瓷。绝缘基体11在为例如氧化铝质烧结体的情况下，通过向氧化铝(Al2O3)、氧化硅(SiO2)、氧化镁(MgO)、氧化钙(CaO)等原料粉末添加混合适当的有机粘结剂以及溶剂等来制作泥浆物。通过采用以往周知的刮板法或压延辊法等使该泥浆物成形为片状来制作陶瓷生片。接着，对该陶瓷生片实施适当的冲裁加工，并且层叠多张陶瓷生片而形成生成形体，以高温(约1600℃)对该生成形体进行烧成来制作绝缘基体11。
凹入部12或腔室16例如可以通过如下方式形成：在绝缘基体11用的陶瓷生片中的几个陶瓷生片进行激光加工或基于模具的冲裁加工等，在各陶瓷生片形成作为凹入部12或腔室16的贯通孔，将该陶瓷生片层叠于未形成贯通孔的其他陶瓷生片。
在绝缘基体11的表面以及内部设置有金属层13、电极14以及布线导体15。电极14与布线导体15用于将电子部件2与模块用基板5电连接。金属层13例如作为用于将盖体4接合于电子部件搭载用基板1的接合部。
金属层13、电极14、布线导体15例如是以钨(W)、钼(Mo)、锰(Mn)、银(Ag)或铜(Cu)等为主要成分的金属粉末化物。例如，在绝缘基体11由氧化铝质烧结体构成的情况下，将向W、Mo或Mn等高熔点金属粉末添加混合适当的有机粘结剂以及溶剂等而得到的金属化糊剂预先通过网版印刷法以规定图案印刷涂布于绝缘基体11用的陶瓷生片，并与绝缘基体11用的陶瓷生片同时地进行烧成，由此被覆形成于绝缘基体11的规定位置。金属层13、电极14、布线导体15例如通过如下方式来形成：通过网版印刷法等印刷手段向绝缘基体11用的陶瓷生片印刷涂布金属层13、电极14、布线导体15用的金属化糊剂，与绝缘基体11用的陶瓷生片一起进行烧成。另外，构成布线导体15的贯通导体例如通过如下方式来形成：通过基于模具或冲孔进行的冲裁加工或激光加工等加工方法来在绝缘基体11用的陶瓷生片形成贯通导体用的贯通孔，通过上述印刷手段向该贯通孔填充贯通导体用的金属化糊剂，与绝缘基体11用的陶瓷生片一起进行烧成。金属化糊剂通过向上述的金属粉末添加适当的溶剂以及粘结剂并混炼而调整为适度的粘度来制作。需要说明的是，为了提高与绝缘基体11的接合强度，也可以包含玻璃粉末、陶瓷粉末。
金属层13在凹入部12与腔室16之间的侧壁上设置为带状。金属层13在图1所示的例子中以包围腔室16的方式设置为框状。金属层13例如用于与盖体4的接合或与金属等的框体、其他构件的接合。
电极14在凹入部12的底面导出，电极14的端部14a延伸至绝缘基体11的内部，即，电极14从凹入部12的底面至绝缘基体11的内部地设置。第一实施方式的电极14例如用作与模块用基板5的连接焊盘51连接的外部电极。当电极14向绝缘基体11的内部延伸的长度、即在俯视透视下与绝缘基体11重叠的长度为50μm以上时，能够良好地提高在凹入部12的底面设置的电极14的强度。如图2所示，当电极14设置为以在俯视下与凹入部12的三边的侧壁分别重叠的方式延伸至绝缘基体11的内部时，能够更加良好地提高电极14的强度。
如图2以及图3所示，电极14的端部14a设置于绝缘基体11的内部，具有向第二主面11b侧倾斜的倾斜部14b。通过采用这样的结构，能够形成如下的电子部件搭载用基板1：该电子部件搭载用基板1能够抑制在例如构成电极14周围的绝缘基体11的绝缘层11c之间设置有空隙的情况，抑制绝缘基体11的内部的电极14周围处的气密性降低，抑制凹入部12周围的气密性降低。
另外，倾斜部14b的前端侧在绝缘基体11的内部比凹入部12的底面向第二主面11b侧倾斜，在纵剖视下，倾斜部14b的前端位于比凹入部12的底面靠第二主面11b侧的位置。另外，与绝缘基体11重叠的长度优选为凹入部12与腔室16之间的侧壁的宽度的30％以下。
这样的倾斜部14b可以通过如下方式形成：预先在成为凹入部12的底面的陶瓷生片上以端部倾斜的方式设置凹陷部，向该凹陷部印刷涂布电极14用的金属化糊剂。另外，在绝缘基体11的第一主面11a与凹入部12的底面的间隔(凹入部12的深度)小的情况下，可以通过如下方式来形成：准备印刷有金属层13用的金属化糊剂的陶瓷生片和印刷有电极14用的金属化糊剂的陶瓷生片，以使金属层13用的金属化糊剂与电极14用的金属化糊剂在俯视下接近的方式层叠陶瓷生片，之后从两主面侧对这些陶瓷生片施加压力，使其埋设于成为凹入部12的底面的陶瓷生片侧。这样，能够形成如下的电子部件搭载用基板1：能够使倾斜部14b处的电极14的厚度薄且高密度地形成，使倾斜部14b的前端埋设于绝缘基体11的第二主面11b侧，使绝缘基体11的内部的电极以及电极14周围处的气密性良好，抑制凹入部12周围的气密性降低。
电极14的端部14a位于在俯视透视下与金属层13重叠的区域。若金属层13与电极14的重叠宽度在俯视透视下为金属层13的宽度的50％以下，则在从两主面侧对陶瓷生片施加压力时，能够向电极14的端部14a良好地传递压力，使其更加良好地埋设于成为凹入部12的底面的陶瓷生片侧。
在金属层13、电极14、布线导体15的从绝缘基体11露出的表面上，通过电镀法或非电解镀法而被覆有金属镀层。金属镀层由镍、铜、金或银等耐腐蚀性以及与连接构件3的连接性优异的金属构成，例如依次被覆厚度0.5～5μm左右的镍镀层和厚度0.1～3μm左右的金镀层，或者依次被覆厚度1～10μm左右的镍镀层和厚度0.1～1μm左右的银镀层。由此，能够有效抑制金属层13、电极14及布线导体15的腐蚀，并且能够使布线导体15与搭接线等连接构件3的接合、电极14与形成于模块用基板5的连接用的连接焊盘51的接合、金属层13与盖体4的接合牢固。
另外，金属镀层并不限定于镍镀层/金镀层、镍镀层/银镀层，也可以是包含镍镀层/金镀层/银镀层、或者镍镀层/钯镀层/金镀层等的其他金属镀层。
另外，也可以是，在搭载电子部件2的布线导体15上，例如将厚度10～80μm左右的铜镀层作为金属镀层而被覆于例如上述的镍镀层和金镀层的基底层，从而容易使电子部件2的热量经由铜镀层而向电子部件搭载用基板1侧良好地散出。
可以将电子部件2搭载于电子部件搭载用基板1的腔室16的底面来制作电子装置。搭载于电子部件搭载用基板1的电子部件2是IC芯片或LSI芯片等半导体元件、发光元件、水晶振子或压电振子等压电元件以及各种传感器等。例如，在电子部件2为引线接合型的半导体元件的情况下，半导体元件通过如下方式搭载于电子部件搭载用基板1：该半导体元件通过低熔点钎料或导电性树脂等接合构件而固定在搭载用金属层上之后，经由搭接线等连接构件3而将半导体元件的电极与布线导体15电连接。由此，电子部件2与电极13电连接。另外，在例如电子部件2为倒装芯片型的半导体元件的情况下，半导体元件通过如下方式搭载于电子部件搭载用基板1：经由焊料凸点、金属凸点或导电性树脂(各向异性导电树脂等)等连接构件3而将半导体元件的电极与布线导体15电连接以及机械连接。另外，在电子部件搭载用基板1上，也可以搭载多个电子部件2，也可以根据需要而搭载电阻元件或容量元件等小型的电子部件。另外，电子部件2根据需要而由盖体4密封，所述盖体4由树脂或玻璃等构成。
例如如图4所示，本实施方式的电子装置的电极14经由焊料6与模块用基板5的连接焊盘51连接而形成电子模块。在电子装置中，例如如图4所示，配置于电子部件搭载用基板1的上表面侧的电极14与模块用基板5的连接焊盘51连接。
本实施方式的电子部件搭载用基板1具有：在俯视下为矩形形状的绝缘基体11，其具有第一主面11a以及与第一主面11a相对的第二主面11b，该绝缘基体11在第一主面11a开口，具有凹入部12；带状的金属层13，其设置于凹入部12的侧壁上；以及电极14，其从凹入部12的底面到绝缘基体11的内部地设置，电极14的端部14a设置于绝缘基体11的内部，端部14a具有向第二主面11b侧倾斜的倾斜部14b。根据上述结构，能够形成如下的电子部件搭载用基板：抑制在例如构成电极14周围的绝缘基体11的绝缘层11c之间设置有空隙的情况，在电极14的端部14a设置有倾斜部14b而使电极14的厚度薄，并将其埋设于绝缘基体11的第二主面11b侧，由此能够抑制绝缘基体11内部的电极14以及电极14周围处的气密性降低，抑制凹入部12周围的气密性降低。
另外，在俯视透视下，通过凹入部12的侧壁与倾斜部14b重叠，能够形成如下的电极14：使倾斜部14b的厚度薄并良好地埋设于绝缘基体11的第二主面11b侧，由此使气密性以及电极14与绝缘基体11的接合强度优异。
另外，若在俯视透视下带状的金属层13与倾斜部14b重叠，则在绝缘基体11的第一主面11a与凹入部12的底面的间隔(凹入部12的深度)小的情况下，准备印刷有金属层13用的金属化糊剂的陶瓷生片与印刷有电极14用的金属化糊剂的陶瓷生片，以金属层13用的金属化糊剂与电极14用的金属化糊剂在俯视下接近的方式层叠陶瓷生片，之后从两主面侧对这些陶瓷生片施加了压力时，能够形成如下的电子部件搭载用基板1：能够使倾斜部14b处的电极14的厚度薄且高密度地形成，将倾斜部14b的前端埋设于绝缘基体11的第二主面11b侧，能够使绝缘基体11内部的电极以及电极14周围处的气密性良好，抑制凹入部12周围的气密性降低。
若金属层13与倾斜部14b的俯视下的重叠部分W为纵剖视下的绝缘基体11的厚度方向上的金属层13与电极14的间隔H以上(W≥H)，则在从两主面侧对这些陶瓷生片施加了压力时，能够良好地从金属层13向电极14的端部传递压力，能够使倾斜部14b处的电极14的厚度薄且高密度地形成，能够将倾斜部14b的前端良好地埋设于绝缘基体11的第二主面11b侧。
另外，若如图3所示的例子那样比电极14靠第一主面11a侧的绝缘层11c的厚度小于比电极14靠第二主面11b侧的绝缘层11c的厚度，则在从两主面侧对这些陶瓷生片施加了压力时，能够更加良好地从金属层13向电极14的端部传递压力，能够将电极14的倾斜部14b的前端良好地埋设于绝缘基体11的第二主面11b侧。
需要说明的是，通过带状的金属层13与倾斜部14b如图2所示的例子那样沿着凹入部12的侧壁呈带状重叠，由此能够形成如下的电子部件搭载用基板1：电极14的端部14a沿着凹入部12的侧壁呈带状地具有倾斜部14b，电极14的端部14a整体以电极14的厚度薄的方式高密度地形成，能够埋设于绝缘基体11的第二主面11b侧，能够使绝缘基体11内部的电极以及电极14周围处的气密性良好，抑制凹入部12周围的气密性降低。
在该情况下，当带状的金属层13的长度L1如图2所示的例子那样比凹入部12的长度L2长(L1＞L2)时，能够更有效地使电极14的端部14a整体以电极14的厚度薄的方式高密度地形成，并埋设于绝缘基体11的第二主面11b侧。
另外，当带状的金属层13的长度L1和电极14的长度L3比凹入部12的长度L2长(L1＞L2且L3＞L2)时，能够在凹入部12与腔室16之间的侧壁整体的范围内使电极14的端部14a整体以电极14的厚度薄的方式高密度地形成，并埋设于绝缘基体11的第二主面11b侧，因此能够形成可使绝缘基体11内部的电极以及电极14周围处的气密性良好且抑制凹入部12周围的气密性降低的电子部件搭载用基板1。需要说明的是，若电极14的长度L3比带状的金属层13的长度L1长(L3＞L1)，则在从两主面侧对陶瓷生片施加压力时，能够沿着金属层13均等地施加，因此是优选的。
另外，当在俯视透视下倾斜部14b的区域包含于凹入部12的侧壁的区域时，通过使倾斜部14b的厚度薄并良好地埋设于绝缘基体11的第二主面11b侧，能够形成气密性以及与绝缘基体11的接合强度优异的电极14。
另外，电极14是与模块用基板5连接的外部电极，绝缘基体11具有侧面，若凹入部12在侧面开口而成为供外部电极经由焊料6与模块用基板5连接的焊料积存部，则在电子装置使用时，即使因电子部件搭载用基板1与模块用基板5之间的热膨胀差而对电极14施加了应力，电极14的连接以及气密性也优异，作为小型的电子部件搭载用基板1而言，能够形成安装可靠性以及气密性优异的基板。
本实施方式的电子装置通过具有上述结构的电子部件搭载用基板1和搭载于电子部件搭载用基板1的电子部件2，由此能够形成长期可靠性优异的电子装置。
另外，在盖体4为透光性且作为电子部件2而使用发光元件等光学元件的情况下，如图4所示，在模块用基板5设置有用于使光透过的开口部52。这样的开口部52在俯视下形成为比电子部件2大。
本实施方式的电子模块通过包括具有连接焊盘51的模块用基板5和经由焊料6而与连接焊盘51连接的上述结构的电子装置，能够形成长期可靠性优异的电子模块。
本实施方式中的电子部件搭载用基板1能够较佳地使用于小型且高输出的电子装置，能够提高电子部件搭载用基板1的连接可靠性。例如，在作为电子部件2而使用发光元件的情况下，能够较佳地用作小型的发光元件搭载用基板。
(第二实施方式)
接着，参照图5～图7来说明本发明的第二实施方式的电子装置。
在本发明的第二实施方式的电子装置中，与上述的第一实施方式的电子装置不同点是凹入部12兼作为搭载电子部件2的腔室16。在图6所示的例子中，将在俯视透视下与凹入部12的内壁面重叠的区域用虚线示出。另外，在图6所示的例子中，将在俯视透视下与布线导体15的贯通导体的侧面重叠的区域用虚线示出。另外，在图6所示的例子中，将在俯视透视下与金属层13的内缘部及外缘部重叠的区域用虚线示出。
就第二实施方式的电子部件搭载用基板1而言，在图1～图3所示的例子中，绝缘基体11由四层绝缘层11c形成，凹入部12设置于第一主面11a侧的第一个绝缘层11c，电极14设置于第一主面11a侧的第二个绝缘层11c的表面。
根据本发明的第二实施方式的电子部件搭载用基板1，与第一实施方式的电子部件搭载用基板1同样，能够形成如下的电子部件搭载用基板：抑制在例如构成电极14周围的绝缘基体11的绝缘层11c之间设置有空隙的情况，在电极14的端部14a设置有倾斜部14b而使电极14的厚度薄，并将其埋设于绝缘基体11的第二主面11b侧，由此能够抑制绝缘基体11内部的电极14以及电极14周围处的气密性降低，抑制凹入部12周围的气密性降低。
在第二实施方式中，电极14是连接电子部件2的连接用电极，凹入部12是经由连接用电极来搭载电子部件2的腔室16，因此能够使凹入部12(腔室16)与绝缘基体11的侧壁之间的气密性优异，因此能够形成对电子部件2的可靠性优异的电子部件搭载用基板1。
在第二实施方式的电子部件搭载用基板1中，当电极14如图5～图7所示的例子那样在整周上与金属层13重叠时，在凹入部12的侧壁整周上，电极14具有设置于绝缘基体11的内部且向第二主面11b侧倾斜的倾斜部14b。这样，能够在凹入部12的侧壁整周的范围使倾斜部14b处的电极14的厚度薄且高密度地形成，将倾斜部14b的前端埋设于绝缘基体11的第二主面11b侧，因此能够形成如下的电子部件搭载用基板1：能够抑制在构成电极14周围的绝缘基体11的绝缘层11c之间设置有空隙的情况，抑制绝缘基体11的内部的电极14周围处的气密性降低，抑制凹入部12周围的气密性降低。
根据第二实施方式的电子部件搭载用基板1，设置于第二主面11b侧的布线导体15成为与模块用基板5连接的外部电极，与模块用基板5的连接焊盘51连接。
第二实施方式的电子部件搭载用基板1可以采用与上述的第一实施方式的电子部件搭载用基板1同样的制造方法来制作。
本发明并不限定于上述的实施方式的例子，能够进行各种变更。例如，绝缘基体11也可以是在俯视下在侧面或角部具有缺口部、倒角部的矩形形状。
在上述的实施方式中，示出了绝缘基体11由三层或四层绝缘层11c构成的例子，但绝缘基体11也可以由两层或五层以上的绝缘层11c构成。
另外，也可以是，在第一实施方式的电子部件搭载用基板1的第二主面11b上粘接在俯视透视下比腔室16大且与绝缘基体11相比热传导率优异的散热基板来提高向第二主面11b侧散热的散热性，从而形成长期可靠性优异的电子部件搭载用基板1、电子装置以及电子模块，所述散热基板例如是铜(Cu)、铜-钨(Cu-W)、铜-钼(Cu-Mo)等的散热基板。
需要说明的是，如图8所示，也可以在腔室16的底面上设置搭载金属层17。这样的搭载金属层17采用与上述的金属层13、电极14、布线导体15同样的材料以及方法而形成在腔室16的底面上。另外，搭载金属层17也可以与布线导体15连接。
另外，如图9以及图10所示，电子部件搭载用基板1也可以在绝缘基体11的两主面具备腔室16(16a、16b)。在该情况下，若如图9以及图10所示的例子那样第二主面11b侧的腔室16b不与电极14的端部14a重叠、即第二主面11b侧的腔室16b的内壁面IL位于比电极14的端部14a靠内侧的位置，则在从两主面侧对这些陶瓷生片施加了压力时，能够使倾斜部14b处的电极14的厚度薄且高密度地形成，能够将倾斜部14b的前端埋设于绝缘基体11的第二主面11b侧。
另外，也可以是将第一实施方式的电子部件搭载用基板1与第二实施方式的电子部件搭载用基板1组合的构造。
另外，电子部件搭载用基板1也可以以多件同时加工电子部件搭载用基板的形态制作。

Claims (8)

1.一种电子部件搭载用基板，其特征在于，具有：
在俯视下呈矩形形状的绝缘基体，其具有第一主面以及与该第一主面相对的第二主面，所述绝缘基体在所述第一主面开口，且具有凹入部；
带状的金属层，其设置于所述凹入部的侧壁上；以及
电极，其从所述凹入部的底面到所述绝缘基体的内部地设置，
该电极的端部设置于所述绝缘基体的内部，所述端部具有向所述第二主面侧倾斜的倾斜部。
2.根据权利要求1所述的电子部件搭载用基板，其特征在于，
在俯视透视下，所述凹入部的侧壁与所述倾斜部重叠。
3.根据权利要求1或2所述的电子部件搭载用基板，其特征在于，
在俯视透视下，所述带状的金属层与所述倾斜部重叠。
4.根据权利要求1或2所述的电子部件搭载用基板，其特征在于，
在俯视透视下，所述倾斜部的区域包含于所述凹入部的侧壁的区域。
5.根据权利要求1或2所述的电子部件搭载用基板，其特征在于，
所述电极是与模块用基板连接的外部电极，
所述绝缘基体具有侧面，
所述凹入部在所述侧面开口，所述凹入部是供所述外部电极经由焊料而与模块用基板连接的焊料积存部。
6.根据权利要求1或2所述的电子部件搭载用基板，其特征在于，
所述电极是连接电子部件的连接用电极，
所述凹入部是经由所述连接用电极来搭载电子部件的腔室。
7.一种电子装置，其特征在于，具有：
权利要求1至6中任一项所述的电子部件搭载用基板；以及
搭载于该电子部件搭载用基板的电子部件。
8.一种电子模块，其特征在于，具有：
模块用基板，其具有连接焊盘；以及
权利要求7所述的电子装置，其经由焊料而与所述连接焊盘连接。
CN201710716548.XA 2016-08-25 2017-08-18 电子部件搭载用基板、电子装置以及电子模块 Active CN107785327B (zh)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP2016164771A JP6767204B2 (ja) 2016-08-25 2016-08-25 電子部品搭載用基板、電子装置および電子モジュール
JP2016-164771 2016-08-25

Publications (2)

Publication Number Publication Date
CN107785327A CN107785327A (zh) 2018-03-09
CN107785327B true CN107785327B (zh) 2020-05-01

Family

ID=61243444

Family Applications (1)

Application Number Title Priority Date Filing Date
CN201710716548.XA Active CN107785327B (zh) 2016-08-25 2017-08-18 电子部件搭载用基板、电子装置以及电子模块

Country Status (3)

Country Link
US (1) US10249564B2 (zh)
JP (1) JP6767204B2 (zh)
CN (1) CN107785327B (zh)

Families Citing this family (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN112166652A (zh) * 2018-05-29 2021-01-01 京瓷株式会社 电子元件搭载用基板、电子装置以及电子模块
WO2020004567A1 (ja) * 2018-06-27 2020-01-02 京セラ株式会社 電子素子搭載用基板、電子装置および電子モジュール
US20220385266A1 (en) * 2019-06-27 2022-12-01 Kyocera Corporation Electronic component housing package, electronic device, and electronic module
DE102020134205A1 (de) * 2020-12-18 2022-06-23 Te Connectivity Germany Gmbh Elektrisches Bauteil, Verfahren zur Vorbereitung eines elektrischen Bauteils auf einen Lötschritt, und Vorrichtung zur Vorbereitung eines elektrischen Bauteils auf einen Lötschritt

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2006049551A (ja) * 2004-08-04 2006-02-16 Ngk Spark Plug Co Ltd セラミック基板の製造方法
CN104412381A (zh) * 2013-01-31 2015-03-11 京瓷株式会社 电子元件搭载用基板、电子装置以及摄像模块
JP5957151B2 (ja) * 2014-05-28 2016-07-27 日本特殊陶業株式会社 配線基板

Family Cites Families (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2003309205A (ja) * 2002-04-15 2003-10-31 Sumitomo Metal Electronics Devices Inc セラミックパッケージ
JP3994936B2 (ja) * 2002-07-16 2007-10-24 株式会社村田製作所 積層型セラミック電子部品およびその製造方法
JP3827623B2 (ja) * 2002-07-26 2006-09-27 京セラ株式会社 半導体素子収納用パッケージおよび半導体装置
JP5418419B2 (ja) * 2010-06-16 2014-02-19 株式会社村田製作所 積層回路基板
CN103535121B (zh) * 2011-05-16 2017-06-20 株式会社村田制作所 陶瓷电子元器件及其制造方法
JP2013070249A (ja) * 2011-09-22 2013-04-18 Kyocera Corp イメージセンサ
US9608020B2 (en) * 2013-10-23 2017-03-28 Kyocera Corporation Imaging element mounting substrate and imaging device

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2006049551A (ja) * 2004-08-04 2006-02-16 Ngk Spark Plug Co Ltd セラミック基板の製造方法
CN104412381A (zh) * 2013-01-31 2015-03-11 京瓷株式会社 电子元件搭载用基板、电子装置以及摄像模块
JP5957151B2 (ja) * 2014-05-28 2016-07-27 日本特殊陶業株式会社 配線基板

Also Published As

Publication number Publication date
CN107785327A (zh) 2018-03-09
US20180061751A1 (en) 2018-03-01
JP2018032773A (ja) 2018-03-01
US10249564B2 (en) 2019-04-02
JP6767204B2 (ja) 2020-10-14

Similar Documents

Publication Publication Date Title
CN107785327B (zh) 电子部件搭载用基板、电子装置以及电子模块
CN110622300B (zh) 电子部件搭载用基板、电子装置以及电子模块
CN114204405A (zh) 光元件搭载用封装件、电子装置以及电子模块
CN107993985B (zh) 电子部件搭载用基板、电子装置以及电子模块
JP7300454B2 (ja) 配線基板、電子装置および電子モジュール
US10985098B2 (en) Electronic component mounting substrate, electronic device, and electronic module
JP6626735B2 (ja) 電子部品搭載用基板、電子装置および電子モジュール
CN108028232B (zh) 布线基板、电子装置以及电子模块
US20180151483A1 (en) Wiring board, electronic device, and electronic module
JP2023071984A (ja) 配線基板、電子装置および電子モジュール
JP2006270082A (ja) 配線基板及びそれを用いた電子装置
JP6780996B2 (ja) 配線基板、電子装置および電子モジュール
CN111033771B (zh) 电子部件搭载用基板、电子装置及电子模块
US11784117B2 (en) Wiring board, electronic device, and electronic module
CN110291628B (zh) 布线基板、电子装置及电子模块
US11742278B2 (en) Wiring substrate, electronic device, and electronic module
CN110326101B (zh) 布线基板、电子装置及电子模块
CN107431047B (zh) 布线基板、电子装置以及电子模块
JP2017063093A (ja) 配線基板、電子装置および電子モジュール
JP6737646B2 (ja) 配線基板、電子装置および電子モジュール
JP6595308B2 (ja) 電子部品搭載用基板、電子装置および電子モジュール
JP6818457B2 (ja) 配線基板、電子装置および電子モジュール
JP2015050313A (ja) 配線基板および電子装置
JP2020102584A (ja) 回路基板および電子部品
JP2015008276A (ja) 配線基板および電子装置

Legal Events

Date Code Title Description
PB01 Publication
PB01 Publication
SE01 Entry into force of request for substantive examination
SE01 Entry into force of request for substantive examination
GR01 Patent grant
GR01 Patent grant