JPWO2006093191A1 - 半導体パッケージ及びその製造方法 - Google Patents
半導体パッケージ及びその製造方法 Download PDFInfo
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- JPWO2006093191A1 JPWO2006093191A1 JP2007505982A JP2007505982A JPWO2006093191A1 JP WO2006093191 A1 JPWO2006093191 A1 JP WO2006093191A1 JP 2007505982 A JP2007505982 A JP 2007505982A JP 2007505982 A JP2007505982 A JP 2007505982A JP WO2006093191 A1 JPWO2006093191 A1 JP WO2006093191A1
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Abstract
Description
2、113;酸化物層
3;金属層
4a、4b、44、102、115;配線層
5a、5b;絶縁層
6、36;電極
7;配線体
8a、8b;ビア
9;アンダーフィル
10;はんだボール
11、103、104;半導体素子
12;封止樹脂層
20、30、40、50;半導体パッケージ
100;半導体装置
101、111;支持基板
105;はんだバンプ
106;パッケージ基板
112;金属層又は窒化物層
114;絶縁層
Claims (26)
- 基板と、前記基板上に形成された酸化物層と、前記酸化物層上に形成され金、白金、パラジウム、ロジウム、ルテニウム、イリジウム及びオスミウムからなる群から選択された少なくとも1種の金属からなる金属層と、前記金属層上に形成され少なくとも1層の配線層を含む配線体と、前記配線体上に搭載された1又は複数の半導体素子と、を有することを特徴とする半導体パッケージ。
- 前記酸化物層と前記金属層との界面は、他の界面よりも密着力が低いことを特徴とする請求項1に記載の半導体パッケージ。
- 前記酸化物層は、TiO2、Ta2O5、Al2O3、SiO2、ZrO2、HfO2、Nb2O5、ペロブスカイト型酸化物及びBi系層状酸化物からなる群から選択された少なくとも1種の酸化物により形成されていることを特徴とする請求項1又は2に記載の半導体パッケージ。
- 前記ペロブスカイト型酸化物は、BaxSr1−xTiO3(但し、0≦x≦1)、PbZrxTi1−xO3(但し、0≦x≦1)及びPb1−yLayZrxTi1−xO3(但し、0≦x≦1且つ0<y<1)からなる群から選択された少なくとも1種の酸化物であることを特徴とする請求項3に記載の半導体パッケージ。
- 前記Bi系層状酸化物は、BaxSr1−xBi2Ta2O9(但し、0≦x≦1)及びBaxSr1−xBi4Ti4O15(但し、0≦x≦1)からなる群から選択された少なくとも1種の酸化物であることを特徴とする請求項3又は4に記載の半導体パッケージ。
- 前記基板は、半導体材料、金属、石英、セラミックス及び樹脂からなる群から選択された1種の材料からなることを特徴とする請求項1乃至5のいずれか1項に記載の半導体パッケージ。
- 前記半導体材料は、シリコン、サファイア及びGaAsからなる群から選択された1種の半導体材料であることを特徴とする請求項6に記載の半導体パッケージ。
- 前記配線体は、前記配線層の上層及び/又は下層に形成された絶縁層を有することを特徴とする請求項1乃至7のいずれか1項に記載の半導体パッケージ。
- 前記配線体は、更に、前記半導体素子が搭載されている面に形成され前記配線層と電気的に接続された電極を有し、前記半導体素子は、低融点金属、導電性樹脂及び金属含有樹脂からなる群から選択された1種の材料により、前記電極と電気的に接続されていることを特徴とする請求項1乃至8のいずれか1項に記載の半導体パッケージ。
- 前記半導体素子は、フリップチップ接続されていることを特徴とする請求項9に記載の半導体パッケージ。
- 更に、前記半導体素子及び前記配線体の前記半導体素子が搭載されている面を封止する封止樹脂層を有することを特徴とする請求項1乃至10のいずれか1項に記載の半導体パッケージ。
- 前記封止樹脂層の厚さは、前記半導体素子の厚さよりも厚いことを特徴とする請求項11に記載の半導体パッケージ。
- 前記封止樹脂層は、シリカフィラーを含むエポキシ樹脂により形成されていることを特徴とする請求項11又は12に記載の半導体パッケージ。
- 基板上に酸化物層を形成する工程と、前記酸化物層上に金、白金、パラジウム、ロジウム、ルテニウム、イリジウム及びオスミウムからなる群から選択された少なくとも1種の金属からなる金属層を形成する工程と、前記金属層上に少なくとも1層の配線層を含む配線体を形成する工程と、前記配線体上に1又は複数の半導体素子を搭載する工程と、を有することを特徴とする半導体パッケージの製造方法。
- 更に、前記酸化物層と前記金属層との界面で剥離する工程を有することを特徴とする請求項14に記載の半導体パッケージの製造方法。
- 前記半導体素子を搭載した後、前記半導体素子及び前記配線体の前記半導体素子が搭載されている面を覆うように封止樹脂層を形成することにより剥離することを特徴とする請求項15に記載の半導体パッケージの製造方法。
- 前記封止樹脂層の厚さを、前記半導体素子の厚さよりも厚くすることを特徴とする請求項16に記載の半導体パッケージの製造方法。
- 前記封止樹脂層を、シリカフィラーを含むエポキシ樹脂により形成することを特徴とする請求項16又は17に記載の半導体パッケージの製造方法。
- 前記酸化物層と前記金属層との界面で剥離した後、前記金属層をパターニングすることにより、配線又は電極を形成することを特徴とする請求項15乃至18のいずれか1項に記載の半導体パッケージの製造方法。
- 前記酸化物層を、TiO2、Ta2O5、Al2O3、SiO2、ZrO2、HfO2、Nb2O5、ペロブスカイト型酸化物及びBi系層状酸化物からなる群から選択された少なくとも1種の酸化物により形成することを特徴とする請求項14乃至19のいずれか1項に記載の半導体パッケージの製造方法。
- 前記ペロブスカイト型酸化物は、BaxSr1−xTiO3(但し、0≦x≦1)、PbZrxTi1−xO3(但し、0≦x≦1)及びPb1−yLayZrxTi1−xO3(但し、0≦x≦1且つ0<y<1)からなる群から選択された少なくとも1種の酸化物であることを特徴とする請求項20に記載の半導体パッケージの製造方法。
- 前記Bi系層状酸化物は、BaxSr1−xBi2Ta2O9(但し、0≦x≦1)及びBaxSr1−xBi4Ti4O15(但し、0≦x≦1)からなる群から選択された少なくとも1種の酸化物であることを特徴とする請求項20又は21に記載の半導体パッケージの製造方法。
- 前記基板は、半導体材料、金属、石英、セラミックス及び樹脂からなる群から選択された1種の材料からなることを特徴とする請求項14乃至22のいずれか1項に記載の半導体パッケージの製造方法。
- 前記半導体材料は、シリコン、サファイア及びGaAsからなる群から選択された1種の半導体材料であることを特徴とする請求項23に記載の半導体パッケージの製造方法。
- 低融点金属、導電性樹脂及び金属含有樹脂からなる群から選択された1種の材料により、前記半導体素子と、前記配線体に設けられ前記配線層と電気的に接続された電極とを相互に接続することを特徴とする請求項14乃至24のいずれか1項に記載の半導体パッケージの製造方法。
- 前記半導体素子を、フリップチップ接続することを特徴とする請求項25に記載の半導体パッケージの製造方法。
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JP4753960B2 (ja) * | 2008-03-31 | 2011-08-24 | 三洋電機株式会社 | 半導体モジュール、半導体モジュールの製造方法 |
JP2009302427A (ja) * | 2008-06-17 | 2009-12-24 | Shinko Electric Ind Co Ltd | 半導体装置および半導体装置の製造方法 |
TWI384603B (zh) * | 2009-02-17 | 2013-02-01 | Advanced Semiconductor Eng | 基板結構及應用其之封裝結構 |
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US9137903B2 (en) | 2010-12-21 | 2015-09-15 | Tessera, Inc. | Semiconductor chip assembly and method for making same |
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US9269681B2 (en) * | 2012-11-16 | 2016-02-23 | Qualcomm Incorporated | Surface finish on trace for a thermal compression flip chip (TCFC) |
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