JPS6355213B2 - - Google Patents

Info

Publication number
JPS6355213B2
JPS6355213B2 JP55105911A JP10591180A JPS6355213B2 JP S6355213 B2 JPS6355213 B2 JP S6355213B2 JP 55105911 A JP55105911 A JP 55105911A JP 10591180 A JP10591180 A JP 10591180A JP S6355213 B2 JPS6355213 B2 JP S6355213B2
Authority
JP
Japan
Prior art keywords
chip
package
semiconductor
chips
pads
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
JP55105911A
Other languages
English (en)
Other versions
JPS5731166A (en
Inventor
Junji Sakurai
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP10591180A priority Critical patent/JPS5731166A/ja
Publication of JPS5731166A publication Critical patent/JPS5731166A/ja
Publication of JPS6355213B2 publication Critical patent/JPS6355213B2/ja
Granted legal-status Critical Current

Links

Classifications

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    • H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H01L25/065—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00
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    • H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H01L25/07—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L29/00
    • H01L25/074—Stacked arrangements of non-apertured devices
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  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Wire Bonding (AREA)
  • Die Bonding (AREA)

Description

【発明の詳細な説明】 本考案は多層半導体ICチツプを設けた半導体
装置の構造に関する。電子計算機或いは各種通信
装置等の電子機器に於ては、半導体装置の実装密
度を向上せしめることが機器の小型化大容量化を
図る上で極めて重要なことである。
そして上記目的のために大規模集積回路
（LSI）等の半導体集積回路（IC）に於て、パツ
ケージ当たりの素子集積度を向上せしめる技術と
して、(1)複数個のLSIチツプを１個の半導体パツ
ケージ内に列設する構造、(2)１チツプの表裏に半
導体素子を形成する構造、(3)LSIチツプを搭載し
た半導体パツケージを積み重ねる構造、(4)LSI上
に形成した絶縁層上に半導体層を形成し、レー
ザ・アニールで該半導体層を単結晶化し、該単結
晶半導体層にLSIを形成する構造（日経エレクト
ロニクス２−18（1980）P82参照）等があるが、
(1)〜(3)の構造に於ては集積度及び機器に対する実
装密度の大幅な向上は期待できず、又(4)の構造に
於ては集積度及び実装密度は大幅に向上するが、
各層の回路端子が表出しないので、各層に形成さ
れているLSIのプロセス機能や回路機能を個々に
検査することが困難であるという問題があつた。
本発明は上記問題点に鑑み、集積回路（IC）
チツプを積層し、パツケージ寸法の拡大すること
を極力抑え且つパツケージ当たりのICの集積度
を大幅に向上せしめ、更にICチツプ毎のプロセ
ス機能及び回路機能を個々に測定することが可能
な構造を有する多層半導体ICチツプをパツケー
ジ内に封入するようにした半導体装置を目的とす
る。
このような目的は本発明によれば多層半導体
ICチツプと半導体パツケージより構成され、多
層半導体ICチツプは表面周辺部にボンデイング
パツドを有する夫々異なる面積のICチツプより
なり、かつ大なる面積のICチツプ上にはそのボ
ンデイングパツドが表出されるように、それより
小なる面積のICチツプが積層され、半導体パツ
ケージはICチツプに略等しい厚さの複数のパツ
ケージ層の積層より構成され、夫々は面積の異な
る開孔部と、該開孔部側の表面周辺部に配列され
た内部パツドとを有し、該内部パツドは接続され
るべきICチツプのボンデイングパツドに対応す
る位置に設けられ、小なる開孔部面積を有するパ
ツケージ層上には、その内部パツドが表出される
ように、それより大なる開孔部面積を有するパツ
ケージ層が積層され、各ICチツプのボンデイン
グパツドが該チツプに対応するパツケージ層の内
部パツドに略同一平面で接続しうる如く、半導体
パツケージの開孔部内に多層半導体ICチツプが
装着されることを特徴とする半導体装置によつて
達成される。
以下本発明を実施例にもとづいて更に説明す
る。第１図は本発明による半導体装置を構成する
多層半導体ICチツプ積層構造の１実施例を上面
図ａ及びＡ−A′矢視断面図ｂで示し、第２図及
び第３図は半導体パツケージの構造及び該パツケ
ージ中に多層半導体ICチツプを実装する場合の
２実施例の断面図を示す。
本発明の半導体装置に使用する多層半導体IC
チツプを構成する各ICチツプでは、通常行われ
る例えばMIS型ICの製造工程に従つて、ゲート
酸化膜、ゲート電極、ソース・ドレイン領域、配
線等の形成が完了せしめられ、外部へ接続するボ
ンデイングパツド部のみを残して上面が燐珪酸ガ
ラス（PSG）等の表面保護絶縁膜で覆われてい
る。なお上記ボンデイングパツド部にはバンプ状
電極が形成される場合もある。
そして例えば第１図ａ及びｂに示すような多層
半導体ICチツプの積層構造に於ては、第１層の
ICチツプ１ａ、第２層のチツプ１ｂ、第３層の
チツプ１ｃ及び第４層のチツプ１ｄの４辺に沿つ
た周辺部に導通所望数のボンデイングパツド２
ａ，２ｂ，２ｃ或いは2dが形成されており、各
層チツプの大きさは、上層のチツプを載せた際に
下層チツプのボンデイングパツドが上層チツプの
周辺部（外側）に表出するように、上層チツプに
なるに従つて順次小さく形成される。なお９は表
面保護絶縁膜を表す。
そしてこれら半導体ICチツプを積層固着する
際の接着層３はシリコン樹脂、エポキシ樹脂或い
はポリ・イミド等の絶縁性樹脂、銀ペースト等の
導電性接着剤或いは金−錫（Au−Su）等の合金
からなるろう材により形成される。なお上記の
中、ろう材を用いて密着を行う際には下層のIC
チツプの表面保護絶縁膜９上に予めAu等からな
るメタライズ層を形成しておく必要があり、又導
電性接着剤或いはろう材を用いて接着する構造で
は、下層チツプの表面保護絶縁膜９に於ける周縁
部以外の所望の場所にコンタクト窓を形成し、前
記導電性接着剤或いはろう材を介して上層チツプ
の所望の領域と縦方向の電気的接続を行なうこと
が出来る。
本発明の半導体装置は上記のような多層半導体
ICチツプを半導体パツケージ内に配設した構造
を有しており、その半導体パツケージの構造及び
パツケージと多層半導体ICチツプとの組み合わ
せの２実施例を第２図、第３図に示す。
第２図においては半導体パツケージ４はパツケ
ージ層４ａ，４ｂ，４ｃが、基板となるパツケー
ジ層４′上に積層された構造となつている。図よ
り明らかな如く、各パツケージ層はそれが接続さ
れるICチツプ１ａ，１ｂ，１ｃに略等しい厚さ
を有する板状絶縁体よりなり、その表面には内部
パツド６ａ，６ｂ，６ｃ及び夫々異なる面積の開
孔部を有し、内部パツドは第１図に示すICチツ
プのボンデイングパツドに対応する位置に配列さ
れている。
第２図において、パツケージ層４′上に、小な
る面積の開孔部を有するパツケージ層４ａが積層
され、その上にそれより大なる開孔部を有するパ
ツケージ層４ｂが積層されるが、その場合パツケ
ージ層４ａの内部パツド６ａは図示の如く表出さ
れる。４ｂ上には４ｃが同様に積層され、内部パ
ツド６ｂ，６ｃは表出されている。
このような半導体パツケージ中に第１図に示す
如き多層半導体ICチツプが組み込まれる。
図において３は接着層であり、絶縁性樹脂、導
電性接着剤或いはろう材等からなつている。
多層半導体ICチツプの各チツプの所望のボン
デイングパツド２ａ，２ｂ、及び２ｃは半導体パ
ツケージ４の内部パツド６ａ，６ｂ或いは６ｃ
と、ワイヤ・ポンデング等の方法により外部導体
であるワイヤー７で接続されている。なお９は表
面保護絶縁膜を示す。
この接続は、ボンデイングパツド２ａと内部パ
ツド６ａ、同じく２ｂと６ｂ、同じく２ｃと６ｃ
といつた具合に、相互に対応する層同志のボンデ
イングパツドと内部パツドとの間で行われてい
る。このためワイヤ７は、その数が多いにもかか
わらず、各層毎に分離されて上下に交叉しない配
置となり、相互間接触を起こし難いように相互の
間隔が確保されている。
この実施例では最上層のチツプ１ｄの所望のボ
ンデイングパツド２ｄとその下層のチツプ１ｃの
所望のボンデイングパツド２ｃとはワイヤ・ボン
デイングにより外部導体７′で接続された構造を
有しており、各チツプに形成された回路を共通の
電源に接続する際等にはこのような外部導体接続
が行われる。なお該構造に於て半導体パツケージ
４の内部パツド６ａ，６ｂ及び６ｃは、それぞれ
対応する多層半導体ICチツプ１ａ，１ｂ及び１
ｃのボンデイングパツド２ａ，２ｂ或いは２ｃと
ほぼ等しい高さに形成されることが望ましい。
又第３図は多層半導体ICチツプをフエース・
ダウン構造で半導体パツケージに搭載する本発明
の半導体装置の他実施例断面図である。
この実施例では半導体パツケージ４は異なる面
積の開孔部を有するパツケージ層４ａ，４ｂ，４
ｃより構成され、各層は対応するICチツプと略
等しい厚さとなつており、かつ第２図の場合と同
様に内部パツド６ａ，６ｂ，６ｃを有している。
なおこの実施例ではパツケージ層４ａの開孔部は
凹部状となつている。
又この実施例ではボンデイングパツド２ａ，２
ｂ，２ｃ部に鉛−錫（Pb−Sn）半田等からなる
バンプ電極８ａ，８ｂ，８ｃを有しており、これ
らのチツプの上面を下に向け、ボンデイングパツ
ド２ａ，２ｂ，２ｃ、は半導体パツケージ４の内
部パツド６ｃ，６ｂ，６ａ上に、バンプ電極８
ａ，８ｂ，８ｃでろう着固定されている。９は表
面保護絶縁膜を示す。なお該構造に於ては各層の
ICチツプの厚さと半導体パツケージの層間間隔
は、ほぼ等しくする必要がある。
以上説明したように本発明の構造を有する半導
体装置に於ては、半導体パツケージ内にICチツ
プの積層された多層半導体ICチツプが固定され
ているので、パツケージ寸法の拡大を極めて小さ
く抑えながらパツケージ当たりの回路密度（集積
度）を大幅に向上せしめることができると同時
に、各ICチツプのボンデイングパツド或いはそ
れに接続された内部配線が個々にパツケージ内に
表出された構造を有するので、該多層半導体IC
チツプの組立てに際してチツプ毎にプロセス機能
及び回路機能を検査することができ製造歩留まり
の向上が図れる。
さらに本発明の半導体装置のパツケージの内部
パツドの部分の構造が多層半導体ICチツプのボ
ンデイングパツドの部分の構造とほぼ対応するよ
うに形成されているので前記チツプの実装が容易
に行える。
又本発明の第２図に示す如き構造に於ては、各
ICチツプのボンデイングパツドが表出しており、
前述のように異層チツプのボンデイングパツド間
を外部導体で接続することが可能である。従つて
該構造の半導体装置の多層半導体ICチツプに於
ては、必ずしも一枚のチツプで回路機能を完成せ
しめる必要はなく、複数枚のチツプにまたがつて
回路機能を形成することができる。
上述の如く本発明によれば多層半導体ICチツ
プの製造歩留まりが向上すると同時に、電子計算
機或いは電子通信装置等の電子機器の小型化、大
容量化が可能となる。
【図面の簡単な説明】
第１図は本発明の半導体装置を構成する多層半
導体ICチツプの実施例を示しａはその上面図、
ｂはそのＡ−A′矢視断面図である。又第２図及
び第３図は同様に本発明の半導体装置を構成する
半導体パツケージの構造とこのパツケージと多層
半導体ICチツプとの組み合わせ構造の２実施例
の断面図である。 図に於て１ａ，１ｂ，１ｃ，１ｄはICチツプ、
２ａ，２ｂ，２ｃ，２ｄはボンデイングパツド、
３は接着層、４は半導体パツケージで４′，４ａ，
４ｂ，４ｃはパツケージ層、６ａ，６ｂ，６ｃは
パツケージの内部パツド、７及び７′は外部導体、
８ａ，８ｂ，８ｃはバンプ電極、９は表面保護絶
縁膜を示す。

Claims (1)

    【特許請求の範囲】
  1. １ 多層半導体ICチツプと半導体パツケージよ
    り構成され、多層半導体ICチツプは表面周辺部
    にボンデイングパツドを有する夫々異なる面積の
    ICチツプよりなり、かつ大なる面積のICチツプ
    上にはそのボンデイングパツドが表出されるよう
    に、それより小なる面積のICチツプが積層され、
    半導体パツケージはICチツプに略等しい厚さの
    複数のパツケージ層の積層より構成され、夫々は
    面積の異なる開孔部と、該開孔部側の表面周辺部
    に配列された内部パツドとを有し、該内部パツド
    は接続されるべきICチツプのボンデイングパツ
    ドに対応する位置に設けられ、小なる開孔部面積
    を有するパツケージ層上には、その内部パツドが
    表出されるように、それより大なる開孔部面積を
    有するパツケージ層が積層され、各ICチツプの
    ボンデイングパツドが該チツプに対応するパツケ
    ージ層の内部パツドに略同一平面で接続しうる如
    く、半導体パツケージの開孔部内に多層半導体
    ICチツプが装着されることを特徴とする半導体
    装置。
JP10591180A 1980-07-31 1980-07-31 Semiconductor device Granted JPS5731166A (en)

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Application Number Priority Date Filing Date Title
JP10591180A JPS5731166A (en) 1980-07-31 1980-07-31 Semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP10591180A JPS5731166A (en) 1980-07-31 1980-07-31 Semiconductor device

Publications (2)

Publication Number Publication Date
JPS5731166A JPS5731166A (en) 1982-02-19
JPS6355213B2 true JPS6355213B2 (ja) 1988-11-01

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ID=14420041

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