JPS634216B2 - - Google Patents

Info

Publication number
JPS634216B2
JPS634216B2 JP56069403A JP6940381A JPS634216B2 JP S634216 B2 JPS634216 B2 JP S634216B2 JP 56069403 A JP56069403 A JP 56069403A JP 6940381 A JP6940381 A JP 6940381A JP S634216 B2 JPS634216 B2 JP S634216B2
Authority
JP
Japan
Prior art keywords
transmission
data
reception
module
request
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
JP56069403A
Other languages
English (en)
Japanese (ja)
Other versions
JPS57185533A (en
Inventor
Shohei Suzuki
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Ltd
Original Assignee
Hitachi Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Ltd filed Critical Hitachi Ltd
Priority to JP56069403A priority Critical patent/JPS57185533A/ja
Publication of JPS57185533A publication Critical patent/JPS57185533A/ja
Publication of JPS634216B2 publication Critical patent/JPS634216B2/ja
Granted legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F15/00—Digital computers in general; Data processing equipment in general
    • G06F15/16—Combinations of two or more digital computers each having at least an arithmetic unit, a program unit and a register, e.g. for a simultaneous processing of several programs
    • G06F15/163—Interprocessor communication
    • G06F15/17—Interprocessor communication using an input/output type connection, e.g. channel, I/O port

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Theoretical Computer Science (AREA)
  • Software Systems (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Computer And Data Communications (AREA)
  • Bidirectional Digital Transmission (AREA)
  • Communication Control (AREA)
JP56069403A 1981-05-11 1981-05-11 Interruption method for transmission control Granted JPS57185533A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP56069403A JPS57185533A (en) 1981-05-11 1981-05-11 Interruption method for transmission control

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP56069403A JPS57185533A (en) 1981-05-11 1981-05-11 Interruption method for transmission control

Publications (2)

Publication Number Publication Date
JPS57185533A JPS57185533A (en) 1982-11-15
JPS634216B2 true JPS634216B2 (cs) 1988-01-28

Family

ID=13401596

Family Applications (1)

Application Number Title Priority Date Filing Date
JP56069403A Granted JPS57185533A (en) 1981-05-11 1981-05-11 Interruption method for transmission control

Country Status (1)

Country Link
JP (1) JPS57185533A (cs)

Families Citing this family (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS62109452A (ja) * 1985-11-07 1987-05-20 Matsushita Graphic Commun Syst Inc デ−タ通信制御装置
JPS63129746A (ja) * 1986-11-20 1988-06-02 Nippon Telegr & Teleph Corp <Ntt> 通信制御処理装置のフレ−ム送信制御方式
JPH02120956A (ja) * 1988-10-28 1990-05-08 Nec Corp 通信制御方式
JP2679775B2 (ja) * 1989-07-31 1997-11-19 三田工業株式会社 Ｃｐｕ間通信方法

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
PANAFACOM OS UAS2ám´-jf¨Þ±lxbýÐálcý¨IOXs¨ *

Also Published As

Publication number Publication date
JPS57185533A (en) 1982-11-15

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