JPS57185533A - Interruption method for transmission control - Google Patents

Interruption method for transmission control

Info

Publication number
JPS57185533A
JPS57185533A JP56069403A JP6940381A JPS57185533A JP S57185533 A JPS57185533 A JP S57185533A JP 56069403 A JP56069403 A JP 56069403A JP 6940381 A JP6940381 A JP 6940381A JP S57185533 A JPS57185533 A JP S57185533A
Authority
JP
Japan
Prior art keywords
transmission
reception
data
interruption
processing
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP56069403A
Other languages
Japanese (ja)
Other versions
JPS634216B2 (en
Inventor
Shohei Suzuki
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Ltd
Original Assignee
Hitachi Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Ltd filed Critical Hitachi Ltd
Priority to JP56069403A priority Critical patent/JPS57185533A/en
Publication of JPS57185533A publication Critical patent/JPS57185533A/en
Publication of JPS634216B2 publication Critical patent/JPS634216B2/ja
Granted legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F15/00—Digital computers in general; Data processing equipment in general
    • G06F15/16—Combinations of two or more digital computers each having at least an arithmetic unit, a program unit and a register, e.g. for a simultaneous processing of several programs
    • G06F15/163—Interprocessor communication
    • G06F15/17—Interprocessor communication using an input/output type connection, e.g. channel, I/O port

Abstract

PURPOSE:To increase the data transmission efficiency, by performing the data transmission request from a master module independently of a reception of response to a transmission data. CONSTITUTION:A transmission program PG49 is started from a transmission data 11 to a master module MDL3, a transmission request processing 13 is executed, a transmission request 19 is given to a transmission/reception MDL5 and the system is in wait state 17 until a transmission request reception end interruption 51 is received. The interruption 51 is given with the end of the processing 47 and the state 17 is released. In the MDL5, a transmission/reception MDLPG10 is executed, a DMA is started and transmission data frames 40-44 are transmitted to a transmission line 7 one after another. When a reception response frame 45 is received via a reception line 8 to the frames 40-42, the PG10 executes a reception response processing 28 and the release of the transmission buffer is communicated to the MDL3 with a reception response interruption 53 and data transmission can continuously be made.
JP56069403A 1981-05-11 1981-05-11 Interruption method for transmission control Granted JPS57185533A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP56069403A JPS57185533A (en) 1981-05-11 1981-05-11 Interruption method for transmission control

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP56069403A JPS57185533A (en) 1981-05-11 1981-05-11 Interruption method for transmission control

Publications (2)

Publication Number Publication Date
JPS57185533A true JPS57185533A (en) 1982-11-15
JPS634216B2 JPS634216B2 (en) 1988-01-28

Family

ID=13401596

Family Applications (1)

Application Number Title Priority Date Filing Date
JP56069403A Granted JPS57185533A (en) 1981-05-11 1981-05-11 Interruption method for transmission control

Country Status (1)

Country Link
JP (1) JPS57185533A (en)

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS62109452A (en) * 1985-11-07 1987-05-20 Matsushita Graphic Commun Syst Inc Data communication control equipment
JPS63129746A (en) * 1986-11-20 1988-06-02 Nippon Telegr & Teleph Corp <Ntt> Frame transmission control system for communication control equipment
JPH02120956A (en) * 1988-10-28 1990-05-08 Nec Corp Communication control system
EP0469168A2 (en) * 1989-07-31 1992-02-05 Mita Industrial Co. Ltd. Arrangement for diagnosing the cause of communication interruption between two CPUS

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
PANAFACOM OS UAS2ám´-jf¨Þ±lxbýÐálcý¨IOXs¨ *

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS62109452A (en) * 1985-11-07 1987-05-20 Matsushita Graphic Commun Syst Inc Data communication control equipment
JPS63129746A (en) * 1986-11-20 1988-06-02 Nippon Telegr & Teleph Corp <Ntt> Frame transmission control system for communication control equipment
JPH02120956A (en) * 1988-10-28 1990-05-08 Nec Corp Communication control system
EP0469168A2 (en) * 1989-07-31 1992-02-05 Mita Industrial Co. Ltd. Arrangement for diagnosing the cause of communication interruption between two CPUS
US5230043A (en) * 1989-07-31 1993-07-20 Mita Industrial Co., Ltd. Arrangement for diagnosing the cause of communication interruption between two cpus

Also Published As

Publication number Publication date
JPS634216B2 (en) 1988-01-28

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