JPS61502294A - - Google Patents

Info

Publication number
JPS61502294A
JPS61502294A JP60501823A JP50182385A JPS61502294A JP S61502294 A JPS61502294 A JP S61502294A JP 60501823 A JP60501823 A JP 60501823A JP 50182385 A JP50182385 A JP 50182385A JP S61502294 A JPS61502294 A JP S61502294A
Authority
JP
Japan
Prior art keywords
substrate
chips
silicon
assembly
holes
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP60501823A
Other languages
English (en)
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority to US06/615,499 priority Critical patent/US4630096A/en
Application filed filed Critical
Publication of JPS61502294A publication Critical patent/JPS61502294A/ja
Application status is Pending legal-status Critical

Links

Classifications

    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/02Containers; Seals
    • H01L23/04Containers; Seals characterised by the shape of the container or parts, e.g. caps, walls
    • H01L23/053Containers; Seals characterised by the shape of the container or parts, e.g. caps, walls the container being a hollow construction and having an insulating or insulated base as a mounting for the semiconductor body
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/12Mountings, e.g. non-detachable insulating substrates
    • H01L23/14Mountings, e.g. non-detachable insulating substrates characterised by the material or its electrical properties
    • H01L23/147Semiconductor insulating substrates
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/52Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/538Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/18High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H01L24/23Structure, shape, material or disposition of the high density interconnect connectors after the connecting process
    • H01L24/24Structure, shape, material or disposition of the high density interconnect connectors after the connecting process of an individual high density interconnect connector
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/18High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H01L2224/23Structure, shape, material or disposition of the high density interconnect connectors after the connecting process
    • H01L2224/24Structure, shape, material or disposition of the high density interconnect connectors after the connecting process of an individual high density interconnect connector
    • H01L2224/241Disposition
    • H01L2224/24135Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/24137Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being arranged next to each other, e.g. on a common substrate
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/18High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H01L2224/23Structure, shape, material or disposition of the high density interconnect connectors after the connecting process
    • H01L2224/24Structure, shape, material or disposition of the high density interconnect connectors after the connecting process of an individual high density interconnect connector
    • H01L2224/241Disposition
    • H01L2224/24151Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/24221Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/24225Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/24227Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation the HDI interconnect not connecting to the same level of the item at which the semiconductor or solid-state body is mounted, e.g. the semiconductor or solid-state body being mounted in a cavity or on a protrusion of the item
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    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805Shape
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    • H01L2224/48091Arched
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    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
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    • H01L2224/484Connecting portions
    • H01L2224/4847Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a wedge bond
    • H01L2224/48472Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a wedge bond the other connecting portion not on the bonding area also being a wedge bond, i.e. wedge-to-wedge
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    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732Location after the connecting process
    • H01L2224/73251Location after the connecting process on different surfaces
    • H01L2224/73265Layer and wire connectors
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    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42Wire connectors; Manufacturing methods related thereto
    • H01L24/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L24/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L29/00Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof; Multistep manufacturing processes therefor
    • H01L29/02Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0657Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape of the body
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
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    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001Technical content checked by a classifier
    • H01L2924/00014Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
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    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01005Boron [B]
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    • H01L2924/01Chemical elements
    • H01L2924/01006Carbon [C]
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    • H01L2924/01Chemical elements
    • H01L2924/01013Aluminum [Al]
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    • H01L2924/01Chemical elements
    • H01L2924/01019Potassium [K]
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    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01027Cobalt [Co]
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    • H01L2924/01033Arsenic [As]
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    • H01L2924/01039Yttrium [Y]
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    • H01L2924/01049Indium [In]
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    • H01L2924/01074Tungsten [W]
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    • H01L2924/01082Lead [Pb]
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    • H01L2924/10Details of semiconductor or other solid state devices to be connected
    • H01L2924/1015Shape
    • H01L2924/10155Shape being other than a cuboid
    • H01L2924/10158Shape being other than a cuboid at the passive surface
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    • H01L2924/10Details of semiconductor or other solid state devices to be connected
    • H01L2924/102Material of the semiconductor or solid state bodies
    • H01L2924/1025Semiconducting materials
    • H01L2924/10251Elemental semiconductors, i.e. Group IV
    • H01L2924/10253Silicon [Si]
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    • H01L2924/10Details of semiconductor or other solid state devices to be connected
    • H01L2924/11Device type
    • H01L2924/12Passive devices, e.g. 2 terminal devices
    • H01L2924/1204Optical Diode
    • H01L2924/12042LASER
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    • H01L2924/10Details of semiconductor or other solid state devices to be connected
    • H01L2924/11Device type
    • H01L2924/14Integrated circuits
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    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151Die mounting substrate
    • H01L2924/153Connection portion
    • H01L2924/1531Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15312Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a pin array, e.g. PGA
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    • H01L2924/15Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181Encapsulation
    • H01L2924/1815Shape
    • H01L2924/1816Exposing the passive side of the semiconductor or solid-state body
    • H01L2924/18162Exposing the passive side of the semiconductor or solid-state body of a chip with build-up interconnect
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    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/19Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
    • H01L2924/1901Structure
    • H01L2924/1904Component type
    • H01L2924/19041Component type being a capacitor
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    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30Technical effects
    • H01L2924/301Electrical effects
    • H01L2924/3011Impedance
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    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30Technical effects
    • H01L2924/35Mechanical effects
    • H01L2924/351Thermal stress
JP60501823A 1984-05-30 1985-04-15 Pending JPS61502294A (ja)

Priority Applications (1)

Application Number Priority Date Filing Date Title
US06/615,499 US4630096A (en) 1984-05-30 1984-05-30 High density IC module assembly

Publications (1)

Publication Number Publication Date
JPS61502294A true JPS61502294A (ja) 1986-10-09

Family

ID=24465648

Family Applications (1)

Application Number Title Priority Date Filing Date
JP60501823A Pending JPS61502294A (ja) 1984-05-30 1985-04-15

Country Status (6)

Country Link
US (1) US4630096A (ja)
EP (1) EP0183722B1 (ja)
JP (1) JPS61502294A (ja)
DE (1) DE3582480D1 (ja)
IT (1) IT1182219B (ja)
WO (1) WO1985005733A1 (ja)

Cited By (3)

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Publication number Priority date Publication date Assignee Title
JP2006270036A (ja) * 2005-02-28 2006-10-05 Sony Corp ハイブリットモジュール及びその製造方法
JP2006270037A (ja) * 2005-02-28 2006-10-05 Sony Corp ハイブリットモジュール及びその製造方法並びにハイブリット回路装置
JP2010251367A (ja) * 2009-04-10 2010-11-04 Shinko Electric Ind Co Ltd 半導体装置及びその製造方法、並びに電子装置

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US4905075A (en) * 1986-05-05 1990-02-27 General Electric Company Hermetic semiconductor enclosure
EP0244767A3 (en) * 1986-05-05 1988-08-03 Silicon Power Corporation Hermetic semiconductor enclosure and process of manufacture
US4745455A (en) * 1986-05-16 1988-05-17 General Electric Company Silicon packages for power semiconductor devices
US4890156A (en) * 1987-03-13 1989-12-26 Motorola Inc. Multichip IC module having coplanar dice and substrate
US4792533A (en) * 1987-03-13 1988-12-20 Motorola Inc. Coplanar die to substrate bond method
US4781775A (en) * 1987-06-01 1988-11-01 Motorola Inc. Coplanar die to substrate bond method
FR2618255A1 (fr) * 1987-07-14 1989-01-20 Gen Electric Bloc de conditionnement pour le montage et l'interconnexion de puces semiconductrices.
US4743568A (en) * 1987-07-24 1988-05-10 Motorola Inc. Multilevel interconnect transfer process
FR2619665B1 (fr) * 1987-08-21 1989-11-17 France Etat Dispositif de commande de l'eclairage de locaux
EP0385979B1 (en) * 1987-10-20 1993-08-11 Irvine Sensors Corporation High-density electronic modules, process and product
US5631447A (en) * 1988-02-05 1997-05-20 Raychem Limited Uses of uniaxially electrically conductive articles
JPH0756887B2 (ja) * 1988-04-04 1995-06-14 株式会社日立製作所 半導体パッケージ及びそれを用いたコンピュータ
JPH079953B2 (ja) * 1988-04-13 1995-02-01 株式会社東芝 半導体装置の製造方法
US5014114A (en) * 1988-09-30 1991-05-07 Harris Corporation High speed, high density semiconductor memory package with chip level repairability
US5122475A (en) * 1988-09-30 1992-06-16 Harris Corporation Method of making a high speed, high density semiconductor memory package with chip level repairability
US5055637A (en) * 1989-05-02 1991-10-08 Hagner George R Circuit boards with recessed traces
US4985601A (en) * 1989-05-02 1991-01-15 Hagner George R Circuit boards with recessed traces
US5098864A (en) * 1989-11-29 1992-03-24 Olin Corporation Process for manufacturing a metal pin grid array package
US5103292A (en) * 1989-11-29 1992-04-07 Olin Corporation Metal pin grid array package
US5006922A (en) * 1990-02-14 1991-04-09 Motorola, Inc. Packaged semiconductor device having a low cost ceramic PGA package
US5081563A (en) * 1990-04-27 1992-01-14 International Business Machines Corporation Multi-layer package incorporating a recessed cavity for a semiconductor chip
GB9014491D0 (en) * 1990-06-29 1990-08-22 Digital Equipment Int Mounting silicon chips
US5241456A (en) * 1990-07-02 1993-08-31 General Electric Company Compact high density interconnect structure
JP2623952B2 (ja) * 1990-10-17 1997-06-25 日本電気株式会社 集積回路パッケージ
JPH06502744A (ja) * 1991-03-27 1994-03-24
US5250843A (en) * 1991-03-27 1993-10-05 Integrated System Assemblies Corp. Multichip integrated circuit modules
EP0547807A3 (en) * 1991-12-16 1993-09-22 General Electric Company Packaged electronic system
US5432999A (en) * 1992-08-20 1995-07-18 Capps; David F. Integrated circuit lamination process
US5323293A (en) * 1992-12-18 1994-06-21 International Business Machines Corporation Arrangement for placing central processors and memory in a cryo cooled chamber
JP3156896B2 (ja) * 1994-01-28 2001-04-16 富士通カンタムデバイス株式会社 半導体装置の製造方法およびかかる製造方法により製造された半導体装置
US5541449A (en) * 1994-03-11 1996-07-30 The Panda Project Semiconductor chip carrier affording a high-density external interface
US5521434A (en) * 1994-10-17 1996-05-28 International Business Machines Corporation Semiconductor chip and electronic module with integrated surface interconnects/components
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IT8548106D0 (it) 1985-05-21
IT1182219B (it) 1987-09-30
WO1985005733A1 (en) 1985-12-19
EP0183722A1 (en) 1986-06-11
US4630096A (en) 1986-12-16
EP0183722A4 (en) 1987-03-12
DE3582480D1 (de) 1991-05-16

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