IT1182219B - Perfezionamento nei moduli di circuiti integrati ad alta densita' e procedimento di fabbricazione - Google Patents

Perfezionamento nei moduli di circuiti integrati ad alta densita' e procedimento di fabbricazione

Info

Publication number
IT1182219B
IT1182219B IT48106/85A IT4810685A IT1182219B IT 1182219 B IT1182219 B IT 1182219B IT 48106/85 A IT48106/85 A IT 48106/85A IT 4810685 A IT4810685 A IT 4810685A IT 1182219 B IT1182219 B IT 1182219B
Authority
IT
Italy
Prior art keywords
substrate
chips
silicon
high density
modules
Prior art date
Application number
IT48106/85A
Other languages
English (en)
Other versions
IT8548106A0 (it
Inventor
James E Drye
Jack A Schroeder
Ii Vern H Winchell
Original Assignee
Motorola Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Motorola Inc filed Critical Motorola Inc
Publication of IT8548106A0 publication Critical patent/IT8548106A0/it
Application granted granted Critical
Publication of IT1182219B publication Critical patent/IT1182219B/it

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/02Containers; Seals
    • H01L23/04Containers; Seals characterised by the shape of the container or parts, e.g. caps, walls
    • H01L23/053Containers; Seals characterised by the shape of the container or parts, e.g. caps, walls the container being a hollow construction and having an insulating or insulated base as a mounting for the semiconductor body
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/12Mountings, e.g. non-detachable insulating substrates
    • H01L23/14Mountings, e.g. non-detachable insulating substrates characterised by the material or its electrical properties
    • H01L23/147Semiconductor insulating substrates
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/52Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/538Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/18High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H01L24/23Structure, shape, material or disposition of the high density interconnect connectors after the connecting process
    • H01L24/24Structure, shape, material or disposition of the high density interconnect connectors after the connecting process of an individual high density interconnect connector
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/18High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H01L2224/23Structure, shape, material or disposition of the high density interconnect connectors after the connecting process
    • H01L2224/24Structure, shape, material or disposition of the high density interconnect connectors after the connecting process of an individual high density interconnect connector
    • H01L2224/241Disposition
    • H01L2224/24135Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/24137Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being arranged next to each other, e.g. on a common substrate
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/18High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H01L2224/23Structure, shape, material or disposition of the high density interconnect connectors after the connecting process
    • H01L2224/24Structure, shape, material or disposition of the high density interconnect connectors after the connecting process of an individual high density interconnect connector
    • H01L2224/241Disposition
    • H01L2224/24151Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/24221Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/24225Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/24227Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation the HDI interconnect not connecting to the same level of the item at which the semiconductor or solid-state body is mounted, e.g. the semiconductor or solid-state body being mounted in a cavity or on a protrusion of the item
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805Shape
    • H01L2224/4809Loop shape
    • H01L2224/48091Arched
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/484Connecting portions
    • H01L2224/4847Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a wedge bond
    • H01L2224/48472Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a wedge bond the other connecting portion not on the bonding area also being a wedge bond, i.e. wedge-to-wedge
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732Location after the connecting process
    • H01L2224/73251Location after the connecting process on different surfaces
    • H01L2224/73265Layer and wire connectors
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42Wire connectors; Manufacturing methods related thereto
    • H01L24/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L24/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/02Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0657Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape of the body
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001Technical content checked by a classifier
    • H01L2924/00014Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01005Boron [B]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01006Carbon [C]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01013Aluminum [Al]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01019Potassium [K]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01027Cobalt [Co]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01033Arsenic [As]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01039Yttrium [Y]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01049Indium [In]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01074Tungsten [W]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01078Platinum [Pt]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01079Gold [Au]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01082Lead [Pb]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10Details of semiconductor or other solid state devices to be connected
    • H01L2924/1015Shape
    • H01L2924/10155Shape being other than a cuboid
    • H01L2924/10158Shape being other than a cuboid at the passive surface
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10Details of semiconductor or other solid state devices to be connected
    • H01L2924/102Material of the semiconductor or solid state bodies
    • H01L2924/1025Semiconducting materials
    • H01L2924/10251Elemental semiconductors, i.e. Group IV
    • H01L2924/10253Silicon [Si]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10Details of semiconductor or other solid state devices to be connected
    • H01L2924/11Device type
    • H01L2924/12Passive devices, e.g. 2 terminal devices
    • H01L2924/1204Optical Diode
    • H01L2924/12042LASER
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10Details of semiconductor or other solid state devices to be connected
    • H01L2924/11Device type
    • H01L2924/14Integrated circuits
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151Die mounting substrate
    • H01L2924/153Connection portion
    • H01L2924/1531Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15312Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a pin array, e.g. PGA
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181Encapsulation
    • H01L2924/1815Shape
    • H01L2924/1816Exposing the passive side of the semiconductor or solid-state body
    • H01L2924/18162Exposing the passive side of the semiconductor or solid-state body of a chip with build-up interconnect
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/19Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
    • H01L2924/1901Structure
    • H01L2924/1904Component type
    • H01L2924/19041Component type being a capacitor
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30Technical effects
    • H01L2924/301Electrical effects
    • H01L2924/3011Impedance
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30Technical effects
    • H01L2924/35Mechanical effects
    • H01L2924/351Thermal stress

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Wire Bonding (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
IT48106/85A 1984-05-30 1985-05-21 Perfezionamento nei moduli di circuiti integrati ad alta densita' e procedimento di fabbricazione IT1182219B (it)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US06/615,499 US4630096A (en) 1984-05-30 1984-05-30 High density IC module assembly

Publications (2)

Publication Number Publication Date
IT8548106A0 IT8548106A0 (it) 1985-05-21
IT1182219B true IT1182219B (it) 1987-09-30

Family

ID=24465648

Family Applications (1)

Application Number Title Priority Date Filing Date
IT48106/85A IT1182219B (it) 1984-05-30 1985-05-21 Perfezionamento nei moduli di circuiti integrati ad alta densita' e procedimento di fabbricazione

Country Status (6)

Country Link
US (1) US4630096A (it)
EP (1) EP0183722B1 (it)
JP (1) JPS61502294A (it)
DE (1) DE3582480D1 (it)
IT (1) IT1182219B (it)
WO (1) WO1985005733A1 (it)

Families Citing this family (77)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4801561A (en) * 1984-07-05 1989-01-31 National Semiconductor Corporation Method for making a pre-testable semiconductor die package
EP0244767A3 (en) * 1986-05-05 1988-08-03 Silicon Power Corporation Hermetic semiconductor enclosure and process of manufacture
US4905075A (en) * 1986-05-05 1990-02-27 General Electric Company Hermetic semiconductor enclosure
US4745455A (en) * 1986-05-16 1988-05-17 General Electric Company Silicon packages for power semiconductor devices
US4890156A (en) * 1987-03-13 1989-12-26 Motorola Inc. Multichip IC module having coplanar dice and substrate
US4792533A (en) * 1987-03-13 1988-12-20 Motorola Inc. Coplanar die to substrate bond method
US4781775A (en) * 1987-06-01 1988-11-01 Motorola Inc. Coplanar die to substrate bond method
FR2618255A1 (fr) * 1987-07-14 1989-01-20 Gen Electric Bloc de conditionnement pour le montage et l'interconnexion de puces semiconductrices.
US4743568A (en) * 1987-07-24 1988-05-10 Motorola Inc. Multilevel interconnect transfer process
FR2619665B1 (fr) * 1987-08-21 1989-11-17 France Etat Dispositif de commande de l'eclairage de locaux
WO1989004113A1 (en) * 1987-10-20 1989-05-05 Irvine Sensors Corporation High-density electronic modules, process and product
US5631447A (en) * 1988-02-05 1997-05-20 Raychem Limited Uses of uniaxially electrically conductive articles
JPH0756887B2 (ja) * 1988-04-04 1995-06-14 株式会社日立製作所 半導体パッケージ及びそれを用いたコンピュータ
JPH079953B2 (ja) * 1988-04-13 1995-02-01 株式会社東芝 半導体装置の製造方法
US5122475A (en) * 1988-09-30 1992-06-16 Harris Corporation Method of making a high speed, high density semiconductor memory package with chip level repairability
US5014114A (en) * 1988-09-30 1991-05-07 Harris Corporation High speed, high density semiconductor memory package with chip level repairability
US4985601A (en) * 1989-05-02 1991-01-15 Hagner George R Circuit boards with recessed traces
US5055637A (en) * 1989-05-02 1991-10-08 Hagner George R Circuit boards with recessed traces
US5103292A (en) * 1989-11-29 1992-04-07 Olin Corporation Metal pin grid array package
US5098864A (en) * 1989-11-29 1992-03-24 Olin Corporation Process for manufacturing a metal pin grid array package
US5006922A (en) * 1990-02-14 1991-04-09 Motorola, Inc. Packaged semiconductor device having a low cost ceramic PGA package
US5081563A (en) * 1990-04-27 1992-01-14 International Business Machines Corporation Multi-layer package incorporating a recessed cavity for a semiconductor chip
GB9014491D0 (en) * 1990-06-29 1990-08-22 Digital Equipment Int Mounting silicon chips
US5241456A (en) * 1990-07-02 1993-08-31 General Electric Company Compact high density interconnect structure
JP2623952B2 (ja) * 1990-10-17 1997-06-25 日本電気株式会社 集積回路パッケージ
US5250843A (en) * 1991-03-27 1993-10-05 Integrated System Assemblies Corp. Multichip integrated circuit modules
JPH06502744A (ja) * 1991-03-27 1994-03-24 インテグレイテッド システム アセンブリース コーポレーション マルチチップ集積回路パッケージ及びモジュール
EP0547807A3 (en) * 1991-12-16 1993-09-22 General Electric Company Packaged electronic system
US5432999A (en) * 1992-08-20 1995-07-18 Capps; David F. Integrated circuit lamination process
US5323293A (en) * 1992-12-18 1994-06-21 International Business Machines Corporation Arrangement for placing central processors and memory in a cryo cooled chamber
JP3156896B2 (ja) * 1994-01-28 2001-04-16 富士通株式会社 半導体装置の製造方法およびかかる製造方法により製造された半導体装置
US5541449A (en) * 1994-03-11 1996-07-30 The Panda Project Semiconductor chip carrier affording a high-density external interface
US5521434A (en) * 1994-10-17 1996-05-28 International Business Machines Corporation Semiconductor chip and electronic module with integrated surface interconnects/components
US5642262A (en) * 1995-02-23 1997-06-24 Altera Corporation High-density programmable logic device in a multi-chip module package with improved interconnect scheme
US5841193A (en) * 1996-05-20 1998-11-24 Epic Technologies, Inc. Single chip modules, repairable multichip modules, and methods of fabrication thereof
US7157314B2 (en) 1998-11-16 2007-01-02 Sandisk Corporation Vertically stacked field programmable nonvolatile memory and method of fabrication
US6392159B1 (en) 1999-07-27 2002-05-21 International Business Machines Corporation Embedded structure for engineering change and repair of circuit boards
US6255899B1 (en) 1999-09-01 2001-07-03 International Business Machines Corporation Method and apparatus for increasing interchip communications rates
US6452265B1 (en) 2000-01-28 2002-09-17 International Business Machines Corporation Multi-chip module utilizing a nonconductive material surrounding the chips that has a similar coefficient of thermal expansion
US8575719B2 (en) 2000-04-28 2013-11-05 Sandisk 3D Llc Silicon nitride antifuse for use in diode-antifuse memory arrays
US6888750B2 (en) 2000-04-28 2005-05-03 Matrix Semiconductor, Inc. Nonvolatile memory on SOI and compound semiconductor substrates and method of fabrication
EP2988331B1 (en) 2000-08-14 2019-01-09 SanDisk Technologies LLC Semiconductor memory device
JP3829050B2 (ja) * 2000-08-29 2006-10-04 松下電器産業株式会社 一体型電子部品
US7352199B2 (en) 2001-02-20 2008-04-01 Sandisk Corporation Memory card with enhanced testability and methods of making and using the same
US6897514B2 (en) 2001-03-28 2005-05-24 Matrix Semiconductor, Inc. Two mask floating gate EEPROM and method of making
US6593624B2 (en) 2001-09-25 2003-07-15 Matrix Semiconductor, Inc. Thin film transistors with vertically offset drain regions
US6843421B2 (en) 2001-08-13 2005-01-18 Matrix Semiconductor, Inc. Molded memory module and method of making the module absent a substrate support
US6841813B2 (en) 2001-08-13 2005-01-11 Matrix Semiconductor, Inc. TFT mask ROM and method for making same
US6525953B1 (en) 2001-08-13 2003-02-25 Matrix Semiconductor, Inc. Vertically-stacked, field-programmable, nonvolatile memory and method of fabrication
US6624485B2 (en) 2001-11-05 2003-09-23 Matrix Semiconductor, Inc. Three-dimensional, mask-programmed read only memory
US6731011B2 (en) 2002-02-19 2004-05-04 Matrix Semiconductor, Inc. Memory module having interconnected and stacked integrated circuits
US6853049B2 (en) 2002-03-13 2005-02-08 Matrix Semiconductor, Inc. Silicide-silicon oxide-semiconductor antifuse device and method of making
JP2004015017A (ja) * 2002-06-11 2004-01-15 Renesas Technology Corp マルチチップモジュールおよびその製造方法
US6737675B2 (en) 2002-06-27 2004-05-18 Matrix Semiconductor, Inc. High density 3D rail stack arrays
US6921975B2 (en) 2003-04-18 2005-07-26 Freescale Semiconductor, Inc. Circuit device with at least partial packaging, exposed active surface and a voltage reference plane
US6838776B2 (en) * 2003-04-18 2005-01-04 Freescale Semiconductor, Inc. Circuit device with at least partial packaging and method for forming
US6849941B1 (en) * 2004-01-07 2005-02-01 Thermagon, Inc. Heat sink and heat spreader assembly
ATE526396T1 (de) * 2004-04-23 2011-10-15 Hema Quebec Verfahren zur expansion von nabelschnurblutzellen
US20050242425A1 (en) * 2004-04-30 2005-11-03 Leal George R Semiconductor device with a protected active die region and method therefor
JP4810957B2 (ja) * 2005-02-28 2011-11-09 ソニー株式会社 ハイブリットモジュール及びその製造方法
JP4810958B2 (ja) * 2005-02-28 2011-11-09 ソニー株式会社 ハイブリット回路装置
JP2008053693A (ja) * 2006-07-28 2008-03-06 Sanyo Electric Co Ltd 半導体モジュール、携帯機器、および半導体モジュールの製造方法
US20080318413A1 (en) * 2007-06-21 2008-12-25 General Electric Company Method for making an interconnect structure and interconnect component recovery process
US9610758B2 (en) * 2007-06-21 2017-04-04 General Electric Company Method of making demountable interconnect structure
US20080318054A1 (en) * 2007-06-21 2008-12-25 General Electric Company Low-temperature recoverable electronic component
US9953910B2 (en) * 2007-06-21 2018-04-24 General Electric Company Demountable interconnect structure
US20080318055A1 (en) * 2007-06-21 2008-12-25 General Electric Company Recoverable electronic component
US20080313894A1 (en) * 2007-06-21 2008-12-25 General Electric Company Method for making an interconnect structure and low-temperature interconnect component recovery process
TWI360207B (en) 2007-10-22 2012-03-11 Advanced Semiconductor Eng Chip package structure and method of manufacturing
JP5372579B2 (ja) * 2009-04-10 2013-12-18 新光電気工業株式会社 半導体装置及びその製造方法、並びに電子装置
US8569894B2 (en) 2010-01-13 2013-10-29 Advanced Semiconductor Engineering, Inc. Semiconductor package with single sided substrate design and manufacturing methods thereof
TWI411075B (zh) 2010-03-22 2013-10-01 Advanced Semiconductor Eng 半導體封裝件及其製造方法
US9406658B2 (en) 2010-12-17 2016-08-02 Advanced Semiconductor Engineering, Inc. Embedded component device and manufacturing methods thereof
US9627395B2 (en) 2015-02-11 2017-04-18 Sandisk Technologies Llc Enhanced channel mobility three-dimensional memory structure and method of making thereof
US9478495B1 (en) 2015-10-26 2016-10-25 Sandisk Technologies Llc Three dimensional memory device containing aluminum source contact via structure and method of making thereof
KR20190013341A (ko) * 2017-08-01 2019-02-11 삼성전자주식회사 열 방출 효율을 향상시킬 수 있는 반도체 패키지
GB2583450B (en) 2019-04-01 2023-04-12 Huber Suhner Polatis Ltd Method and apparatus for suction alignment

Family Cites Families (36)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
FR1355034A (fr) * 1963-02-01 1964-03-13 Crouzet S A R L Nouveau mode de construction d'ensembles comportant des éléments à conductibilité asymétrique et analogues
US3698082A (en) * 1966-04-25 1972-10-17 Texas Instruments Inc Complex circuit array method
US3365620A (en) * 1966-06-13 1968-01-23 Ibm Circuit package with improved modular assembly and cooling apparatus
DE1915501C3 (de) * 1969-03-26 1975-10-16 Siemens Ag, 1000 Berlin Und 8000 Muenchen Verfahren zum Verbinden einer integrierten Schaltung mit äußeren elektrischen Zuleitungen
US3757175A (en) * 1971-01-06 1973-09-04 Soo Kim Chang Tor chips mounted on a single substrate composite integrated circuits with coplnaar connections to semiconduc
US3968193A (en) * 1971-08-27 1976-07-06 International Business Machines Corporation Firing process for forming a multilayer glass-metal module
US3823467A (en) * 1972-07-07 1974-07-16 Westinghouse Electric Corp Solid-state circuit module
US4017886A (en) * 1972-10-18 1977-04-12 Hitachi, Ltd. Discrete semiconductor device having polymer resin as insulator and method for making the same
US3777221A (en) * 1972-12-18 1973-12-04 Ibm Multi-layer circuit package
JPS49131863U (it) * 1973-03-10 1974-11-13
GB1445591A (en) * 1973-03-24 1976-08-11 Int Computers Ld Mounting integrated circuit elements
DE2425626A1 (de) * 1974-05-27 1975-12-11 Standard Elektrik Lorenz Ag Flachgepackte verkapselte festkoerperbauelemente
US3936866A (en) * 1974-06-14 1976-02-03 Northrop Corporation Heat conductive mounting and connection of semiconductor chips in micro-circuitry on a substrate
US4167647A (en) * 1974-10-02 1979-09-11 Santa Barbara Research Center Hybrid microelectronic circuit package
US4189825A (en) * 1975-06-04 1980-02-26 Raytheon Company Integrated test and assembly device
US3984620A (en) * 1975-06-04 1976-10-05 Raytheon Company Integrated circuit chip test and assembly package
JPS5346669A (en) * 1976-10-07 1978-04-26 Satoru Takahashi Switch mechanism operated by bank and lateral g
IT1125182B (it) * 1976-12-14 1986-05-14 Selenia Ind Elettroniche Procedimento per la realizzazione di rivelatori per infrarossi a multielementi del tipo lineare e bidimensionale aventi caratteristiche geometriche perfezionate ed alto grado di integrazione
US4256532A (en) * 1977-07-05 1981-03-17 International Business Machines Corporation Method for making a silicon mask
US4285002A (en) * 1978-01-19 1981-08-18 International Computers Limited Integrated circuit package
GB1556397A (en) * 1978-05-06 1979-11-21 Aei Semiconductors Ltd High power semiconductor devices
FR2435883A1 (fr) * 1978-06-29 1980-04-04 Materiel Telephonique Circuit integre hybride et son procede de fabrication
US4259684A (en) * 1978-10-13 1981-03-31 The Secretary Of State For Defence In Her Britannic Majesty's Government Of The United Kingdom Of Great Britain And Northern Ireland Packages for microwave integrated circuits
FR2439478A1 (fr) * 1978-10-19 1980-05-16 Cii Honeywell Bull Boitier plat pour dispositifs a circuits integres
US4199380A (en) * 1978-11-13 1980-04-22 Motorola, Inc. Integrated circuit method
US4221047A (en) * 1979-03-23 1980-09-09 International Business Machines Corporation Multilayered glass-ceramic substrate for mounting of semiconductor device
US4283754A (en) * 1979-03-26 1981-08-11 Bunker Ramo Corporation Cooling system for multiwafer high density circuit
FR2455785A1 (fr) * 1979-05-02 1980-11-28 Thomson Csf Support isolateur electrique, a faible resistance thermique, et embase ou boitier pour composant de puissance, comportant un tel support
US4245273A (en) * 1979-06-29 1981-01-13 International Business Machines Corporation Package for mounting and interconnecting a plurality of large scale integrated semiconductor devices
US4319265A (en) * 1979-12-06 1982-03-09 The United States Of America As Represented By The Secretary Of The Army Monolithically interconnected series-parallel avalanche diodes
GB2083285B (en) * 1980-02-12 1984-08-15 Mostek Corp Over/under dual in-line chip package
US4396936A (en) * 1980-12-29 1983-08-02 Honeywell Information Systems, Inc. Integrated circuit chip package with improved cooling means
US4407007A (en) * 1981-05-28 1983-09-27 International Business Machines Corporation Process and structure for minimizing delamination in the fabrication of multi-layer ceramic substrate
JPS5843554A (ja) * 1981-09-08 1983-03-14 Mitsubishi Electric Corp 半導体装置
DE3234744C2 (de) * 1982-09-20 1984-11-22 Siemens AG, 1000 Berlin und 8000 München Einrichten zum Halten mehrerer, jeweils mit integrierten Schaltkreisen versehenen Halbleiterplättchen beim Kontaktieren mit auf einem filmförmigen Substrat ausgebildeten Streifenleitern
JPH05346669A (ja) * 1991-05-02 1993-12-27 Eiteku:Kk ピン孔形成方法

Also Published As

Publication number Publication date
JPS61502294A (ja) 1986-10-09
US4630096A (en) 1986-12-16
DE3582480D1 (de) 1991-05-16
IT8548106A0 (it) 1985-05-21
EP0183722B1 (en) 1991-04-10
WO1985005733A1 (en) 1985-12-19
EP0183722A4 (en) 1987-03-12
EP0183722A1 (en) 1986-06-11

Similar Documents

Publication Publication Date Title
IT1182219B (it) Perfezionamento nei moduli di circuiti integrati ad alta densita' e procedimento di fabbricazione
US4975765A (en) Highly integrated circuit and method for the production thereof
JPS57207356A (en) Semiconductor device
AU714028B2 (en) Semiconductor device mounting method and multi-chip module produced by the same
IE830584L (en) Dense mounting of semiconductor chip packages
DE69132880T2 (de) Halbleiterchipanordnungen, herstellungsmethoden und komponenten für dieselben
TW270228B (en) Semiconductor chip and electronic module with integrated surface interconnects/components and fabrication methods therefore
JPS55121670A (en) Chip package for vertical semiconductor integrated circuit
EP1189273A3 (en) Semiconductor device and production process
IT1173777B (it) Modulo di circuito integrato e procedimento per fabbricarlo
US4949220A (en) Hybrid IC with heat sink
GB2137807B (en) A semiconductor component and method of manufacture
GB2083285A (en) Over/under dual in-line chip package
US4717988A (en) Universal wafer scale assembly
JPS56161696A (en) Board
JP2000504490A (ja) 絶縁基板上に高周波バイポーラトランジスタを備える半導体装置
FR2282720B1 (it)
HK40494A (en) Circuit assembly e.g. for an electronic timepiece
TR22767A (tr) Mikrominyatuer baglantilar icin sikistirici kaide
JPS62134957A (ja) 半導体装置
JPS56140637A (en) Semiconductor device
JPS577148A (en) Semiconductor module
JPS6433955A (en) Lead frame
JPS56120147A (en) Integrated circuit package
Sinnadurai et al. The manufacture and reliability of the EPIC chip carrier

Legal Events

Date Code Title Description
TA Fee payment date (situation as of event date), data collected since 19931001

Effective date: 19940720