JPS5843554A - 半導体装置 - Google Patents

半導体装置

Info

Publication number
JPS5843554A
JPS5843554A JP56141985A JP14198581A JPS5843554A JP S5843554 A JPS5843554 A JP S5843554A JP 56141985 A JP56141985 A JP 56141985A JP 14198581 A JP14198581 A JP 14198581A JP S5843554 A JPS5843554 A JP S5843554A
Authority
JP
Japan
Prior art keywords
conductive path
substrates
semiconductor
silicon
substrate
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP56141985A
Other languages
English (en)
Inventor
Hiroshi Shibata
浩 柴田
Hidefumi Nakada
中田　秀文
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Mitsubishi Electric Corp
Original Assignee
Mitsubishi Electric Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Mitsubishi Electric Corp filed Critical Mitsubishi Electric Corp
Priority to JP56141985A priority Critical patent/JPS5843554A/ja
Priority to DE19823233195 priority patent/DE3233195A1/de
Publication of JPS5843554A publication Critical patent/JPS5843554A/ja
Pending legal-status Critical Current

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    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
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Abstract

(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。

Description

【発明の詳細な説明】 この発明は機能素子を３次元的に積み重ねて、単位面積
当９の集積度を高密度化することができる半導体装置に
関するものである。
第１図は従来の半導体装置を示す断面側面図である。同
図に゛おいて、口）はセラミクク基板あるいはプラスチ
ックパッケージ、（２）はこのセラミック基板条゛る−
はプラスチックパッケージ（１）上に形成したメモリあ
るｉは論理回路を形成したチ□ツブ、（３）は内部リー
ド、（４）はチップ（２１＆Ｃ形成し九内示せぬアルミ
ニウムなどの電極パッドと内部リード（３）とを接続す
る金ＩＩＩるいはアルミニウム、ｌＩなど？接続リード
、（５）は前記内部リード（３１に接続する外部リード
、（６）２社對着蓋で条、る。
このよう忙、従来の半導体装置ではｌチップをｌセラミ
ック容器あるいは６１プラスチツクパツケージ内に収納
す今チ、のである。↑こで、多数のチップを１株の上２
゜ミツクモジュールなどに収納して夷４装密度を上げる
方法も実用化されている。しかし、この方法は平面上（
、できるだけ多く＊Ｉ／Ｃ配列して、！装密度を≠げる
もの工東るため、その高密度化に＠度がある矢車があっ
た。
したがって、仲の発明−の目的は半導体基板を三次元的
に一層して１．単位ｍｑ当り９集積度を竺密度化する半
導体装置を提供するもの！ある。−このような目的を達
成するため、この発明悼半導体基、板の深さ方向に１こ
の半導体基板を貫通する拡散層の！導！路を形成し、上
下方整積層し　　　　。
た半導体基板の所定導体間を前記、電導経路によって電
気的ＫＷｋ続するものであり、以下実施例を用いて詳細
に説明する。
第２図はこの発明に係る半導体装置の一実施例を示す概
略断面図である。同図において、（７）はセラミック基
板、（８）はこのセラミック基板（７）Ｋ形成したスル
ーホール、　（９）はこのスルーホール（８）Ｋ接続し
、前記セラミック倉敷（７）に固着した外部り一ドｉｓ
、　ａのはこのスルーホール（８）に接続し、前記セラ
ミック基板（７）に固着したランド、（１１−１）〜Ｑ
ｔ−ｎ）は例えばメモリ回路を形成した半導体基板、ａ
３は仁の半導体基板（１１−１’）〜（１１−ｍ）のそ
れぞれに形成した拡散層の電導経路、Ｉはこの半導体基
１１（ｎ−１）〜（１１−ｎ）間に設け、その電導経路
０２間を電気的に接続する半日また＃′ｉＡｏ′のバン
プである。
なお、前記半導体基板（ｎ−ｔ　）〜（１１−ｍ　）　
Ｋ拡散層の電導経路ａ−影形成る方法について第３図を
参照して説明する。まず、π形あるいは高抵抗のｎ１１
゜ 形シリコン基板（１４１の全面＜５１ｏｚ１にどの酸化
膜αりを形成したのち、拡散竺、４１．〒導経路を形成
する必要とする部分の表裏面に両麺マスク合せ装置など
を用いて酸化膜ａうを除去する。そして、この酸化膜α
埼を除去し大部分から比較的拡散係数の大きいアルミニ
ウムなどを選択拡散して、１形シリコン基板Ｉの表裏両
面よシ深さ方向＜ｐ形の電導経路ａ々を形成することが
できる。この電導経路ａ擾はｐ影領域になるが、基板が
に型あるいけ聰形のため、基板に対して負の電位である
限り、逆バイアス状態となって、電流が流れないので、
電導経路となる。しかし、例えばｎチャンネルＭＯ８）
ッンシスタによって集積回路が形成される場合、基板は
通常ｐ形でなければならないので％第４図に示すように
、この電導経路を除いて、活性領域−をｐ形にする。例
えばｐ形不純物のイオン打込み、あるいはｐ形不純物の
拡散によって、ｐ形層を容易に形成することができる。
また、電導経路ａ３の終端は第５図に示すように、電導
経路α３となる拡散領域上にアルミニウム電極αでおよ
びＣｒ／ＣＩｌ　ＩＩ　０１を、ぺ） 形成したのち、デンゾ０を形成し、酸化ａｒｔｓ上に保
１ｉ１［（８１０２，８ｊ””５Ｎｎ）（ｌｓｔＪｔＪ
ｔｔ　ル。ソシテ、このように、電導経−αりを形成し
たシリコンチップを２枚積層する場合には第６図に示す
ようｋ、両面位置合せ装置などによって、対向するバン
プ峙同志を接続する。また、第７図伽）および第７９伽
）は共に電−経路ａ３を形成する他の方法を示す断面図
である。この方法は電導経−路を形成しようとする位置
に１シリコン基板ａ◆の裏面から、シリコンエツチング
を施こし、部分的に厚みの薄い領域をつくり、できる限
り拡散層の電゛導経路（Ｉのを薄くすることによって、
横方向の拡散層−１１１りを少なく讐るもめである。こ
の場合、電導経路の厚みが薄いため、ｐ形のシリコン基
′ｌｌＬａ４に比゛較゛的拡散係数の小さなａ形不純物
であるＰ（りん）やＡｓ（砒素）をイオン注入ｉるいは
熱拡散によって導入することかできる。この場合も、第
５図に示すように、−通ずる電導経路の両端に、例えば
半田あるいは金などの金属によるパンチを形成し、上層
および下層のシリコン基板Ｉｅ）キップとを電気的に接
続することができる。また、仁の電導経路の他の形成方
法′としては拡散による横方向へめ拡がシをなくすため
、電界中で拡散層せて、拡散の方向を縦方向にの与増達
させてもよいことはもちろんである。
このように、半導体基板に１その保さ方向に貫通する電
導経路を形成し、その上にＩ（ンプａＪを設は九ので、
第２図に示すように１半導体基板（１１−１）〜（１１
−ｎ）をＮ枚積層しても、その半導体基偉間は第６図、
第７図（１）あるいは第７図（ｂ）　Ｋ示すように相互
に接続することができる。　　　　　　　　−なお、上
記、実施例では積層する半導体基板の枚数をＮとしたが
、Ｎ＝２以上であれば任意の数でよい仁とはもちろんで
ある。また、３シリコン基板を基体とする集積回路にメ
モリ回路を、設ける場合について説明したが、ＧａＡｌ
１などの化合物半導体を基板とする集積回路につ諭ても
同様忙できることはもちろんである。
以上１１、詳細に説明したように、この発明に係る半導
体装置によれば■配線長が短かくなるので、浮遊容量が
低下し、高速化が可能になる％俤）各層の半導体基板が
チップの段階でテストができるため、良品チップである
ことを確認できるので、Ｎ枚積層しても良品率を高く維
持することができる、（ｑフリップ・チップ・ポンディ
ングであるから、配線接続の信頼性が高く、コストの低
減に適する、（ロ）シリコン基板などの半導体基板を任
意の数だけ積層することができるため、単位面積当シの
集積度を高密度化することができ、システム自体の容積
を小さくすることができるなどの効果がある。
【図面の簡単な説明】
第１図は従来の半導体装置を示す断面側面図、第２図は
この発明に係る半導体装置の一実施例を示す概略断面図
、第３図は第２図の電導経路の形成方法を説明する丸め
の図、第４図はｇ形あるいは態形のシリコン基板に電導
経路を形成する場合を示す図、第５図は第２図の電導経
路の詳細な断面図、第６図は２枚のシリコンチップを積
層した場合を示す詳細な断面図、第７図（りおよび第７
図会）は１それぞれ２枚のシ１７　ｐンチップを積層し
た−の例を示す断面図である二セ １； （１）ＩＩ・・・セラミック邊、、板あるいはプラスチ
ックパッケージ、（２）・・・・ゝチップ、（３）・・
・・内部リード、（４）・・・・金−、（５Ｊ＠・・・
外部リード、１６）・・・・封止蓋、（７）・・・・セ
ラミック基１１、＋８１・・・・スルーホール、＋９）
・・・＝外部リード線、（ＩＩ・・・・ランド、（１１
−１）〜（１１−ｎ）　・・・・半導体基板、ａ々・・
・・電導経路、ｕ３・・・・バンプ、Ｉ・・・・シリコ
ン基１ｊ、　ａ！９・・・・酸化膜、（ｌＧ・・・・活
性領域、（ｉｆ）・・・・アルミニウム電極、晴・・・
・Ｃｒ　ＺＣｕ展、Ｑｌ・・・・保護膜。 なお、同一符号は同一または相当部分を示す。 代理人　・葛　野　信　−（外１名） □ ・； ・ξ １１．８ ．５．・ ′） 第１図 第３図 第２図 １フ 第５図 １３ 第・７図　　　　− （ａ） １ □！

Claims (1)

    【特許請求の範囲】
  1. 半導体基板の深さ方向に１この半導体基板を貫通する拡
    散層の電導経路を形成し、上下方向に積層した半導体基
    板の所定導体間を前配電導経路忙よって電気的に接続し
    、半導体基板を三次元的に積み重ね九ことを特徴とする
    半導体装置。
JP56141985A 1981-09-08 1981-09-08 半導体装置 Pending JPS5843554A (ja)

Priority Applications (2)

Application Number Priority Date Filing Date Title
JP56141985A JPS5843554A (ja) 1981-09-08 1981-09-08 半導体装置
DE19823233195 DE3233195A1 (de) 1981-09-08 1982-09-07 Halbleitervorrichtung

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP56141985A JPS5843554A (ja) 1981-09-08 1981-09-08 半導体装置

Publications (1)

Publication Number Publication Date
JPS5843554A true JPS5843554A (ja) 1983-03-14

Family

ID=15304710

Family Applications (1)

Application Number Title Priority Date Filing Date
JP56141985A Pending JPS5843554A (ja) 1981-09-08 1981-09-08 半導体装置

Country Status (2)

Country Link
JP (1) JPS5843554A (ja)
DE (1) DE3233195A1 (ja)

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JPS59224143A (ja) * 1983-06-03 1984-12-17 Agency Of Ind Science & Technol 半導体装置の製造方法
JPS62216258A (ja) * 1986-03-17 1987-09-22 Agency Of Ind Science & Technol 三次元組立集積回路
US4807021A (en) * 1986-03-10 1989-02-21 Kabushiki Kaisha Toshiba Semiconductor device having stacking structure
US5202754A (en) * 1991-09-13 1993-04-13 International Business Machines Corporation Three-dimensional multichip packages and methods of fabrication
US5504035A (en) * 1989-08-28 1996-04-02 Lsi Logic Corporation Process for solder ball interconnecting a semiconductor device to a substrate using a noble metal foil embedded interposer substrate
WO1996013062A1 (en) * 1994-10-19 1996-05-02 Ceram Incorporated Apparatus and method of manufacturing stacked wafer array
US5841197A (en) * 1994-11-18 1998-11-24 Adamic, Jr.; Fred W. Inverted dielectric isolation process
US5888853A (en) * 1997-08-01 1999-03-30 Advanced Micro Devices, Inc. Integrated circuit including a graded grain structure for enhanced transistor formation and fabrication method thereof
US5898189A (en) * 1997-08-04 1999-04-27 Advanced Micro Devices, Inc. Integrated circuit including an oxide-isolated localized substrate and a standard silicon substrate and fabrication method
US5949092A (en) * 1997-08-01 1999-09-07 Advanced Micro Devices, Inc. Ultra-high-density pass gate using dual stacked transistors having a gate structure with planarized upper surface in relation to interlayer insulator
US5994763A (en) * 1997-06-30 1999-11-30 Oki Electric Industry Co., Ltd. Wiring structure for semiconductor element and method for forming the same
US6069398A (en) * 1997-08-01 2000-05-30 Advanced Micro Devices, Inc. Thin film resistor and fabrication method thereof
WO2000036650A1 (fr) * 1998-12-16 2000-06-22 Seiko Epson Corporation Puce de semi-conducteur, dispositif a semi-conducteur, carte de circuits et materiel electronique et leurs procedes de production
US6124179A (en) * 1996-09-05 2000-09-26 Adamic, Jr.; Fred W. Inverted dielectric isolation process
US6642615B2 (en) 2000-02-28 2003-11-04 Seiko Epson Corporation Semiconductor device and method of manufacturing the same, circuit board and electronic instrument
JP2006352171A (ja) * 1998-12-16 2006-12-28 Seiko Epson Corp 半導体チップの製造方法、半導体装置の製造方法、回路基板の製造方法及び電子機器の製造方法

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US5354695A (en) 1992-04-08 1994-10-11 Leedy Glenn J Membrane dielectric isolation IC fabrication
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US5399898A (en) * 1992-07-17 1995-03-21 Lsi Logic Corporation Multi-chip semiconductor arrangements using flip chip dies
US5032896A (en) * 1989-08-31 1991-07-16 Hughes Aircraft Company 3-D integrated circuit assembly employing discrete chips
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* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS59224143A (ja) * 1983-06-03 1984-12-17 Agency Of Ind Science & Technol 半導体装置の製造方法
US4807021A (en) * 1986-03-10 1989-02-21 Kabushiki Kaisha Toshiba Semiconductor device having stacking structure
JPS62216258A (ja) * 1986-03-17 1987-09-22 Agency Of Ind Science & Technol 三次元組立集積回路
JPH0358543B2 (ja) * 1986-03-17 1991-09-05 Kogyo Gijutsu Incho
US5504035A (en) * 1989-08-28 1996-04-02 Lsi Logic Corporation Process for solder ball interconnecting a semiconductor device to a substrate using a noble metal foil embedded interposer substrate
US5202754A (en) * 1991-09-13 1993-04-13 International Business Machines Corporation Three-dimensional multichip packages and methods of fabrication
WO1996013062A1 (en) * 1994-10-19 1996-05-02 Ceram Incorporated Apparatus and method of manufacturing stacked wafer array
US5841197A (en) * 1994-11-18 1998-11-24 Adamic, Jr.; Fred W. Inverted dielectric isolation process
US6124179A (en) * 1996-09-05 2000-09-26 Adamic, Jr.; Fred W. Inverted dielectric isolation process
US5994763A (en) * 1997-06-30 1999-11-30 Oki Electric Industry Co., Ltd. Wiring structure for semiconductor element and method for forming the same
US5949092A (en) * 1997-08-01 1999-09-07 Advanced Micro Devices, Inc. Ultra-high-density pass gate using dual stacked transistors having a gate structure with planarized upper surface in relation to interlayer insulator
US6069398A (en) * 1997-08-01 2000-05-30 Advanced Micro Devices, Inc. Thin film resistor and fabrication method thereof
US5888853A (en) * 1997-08-01 1999-03-30 Advanced Micro Devices, Inc. Integrated circuit including a graded grain structure for enhanced transistor formation and fabrication method thereof
US5898189A (en) * 1997-08-04 1999-04-27 Advanced Micro Devices, Inc. Integrated circuit including an oxide-isolated localized substrate and a standard silicon substrate and fabrication method
WO2000036650A1 (fr) * 1998-12-16 2000-06-22 Seiko Epson Corporation Puce de semi-conducteur, dispositif a semi-conducteur, carte de circuits et materiel electronique et leurs procedes de production
US6424048B1 (en) 1998-12-16 2002-07-23 Seiko Epson Corporation Semiconductor chip, semiconductor device, circuit board and electronic equipment and production methods for them
US6677237B2 (en) 1998-12-16 2004-01-13 Seiko Epson Corporation Semiconductor chip, semiconductor device, circuit board and electronic equipment and production methods for them
JP2006352171A (ja) * 1998-12-16 2006-12-28 Seiko Epson Corp 半導体チップの製造方法、半導体装置の製造方法、回路基板の製造方法及び電子機器の製造方法
JP4497147B2 (ja) * 1998-12-16 2010-07-07 セイコーエプソン株式会社 半導体チップの製造方法、半導体装置の製造方法、回路基板の製造方法及び電子機器の製造方法
US6642615B2 (en) 2000-02-28 2003-11-04 Seiko Epson Corporation Semiconductor device and method of manufacturing the same, circuit board and electronic instrument

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