JPS6131627B2 - - Google Patents

Info

Publication number
JPS6131627B2
JPS6131627B2 JP52147662A JP14766277A JPS6131627B2 JP S6131627 B2 JPS6131627 B2 JP S6131627B2 JP 52147662 A JP52147662 A JP 52147662A JP 14766277 A JP14766277 A JP 14766277A JP S6131627 B2 JPS6131627 B2 JP S6131627B2
Authority
JP
Japan
Prior art keywords
island
lead frame
lead
punch
semiconductor
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
JP52147662A
Other languages
English (en)
Other versions
JPS5479563A (en
Inventor
Seiji Inaba
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Kyushu Ltd
Original Assignee
NEC Kyushu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Kyushu Ltd filed Critical NEC Kyushu Ltd
Priority to JP14766277A priority Critical patent/JPS5479563A/ja
Priority to US05/966,861 priority patent/US4258381A/en
Publication of JPS5479563A publication Critical patent/JPS5479563A/ja
Publication of JPS6131627B2 publication Critical patent/JPS6131627B2/ja
Granted legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/40—Leadframes
    • H10W70/411—Chip-supporting parts, e.g. die pads
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/40—Leadframes
    • H10W70/421—Shapes or dispositions
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/30—Die-attach connectors
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/50—Bond wires
    • H10W72/541—Dispositions of bond wires
    • H10W72/5449—Dispositions of bond wires not being orthogonal to a side surface of the chip, e.g. fan-out arrangements
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/90—Bond pads, in general
    • H10W72/931—Shapes of bond pads
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H10W90/751—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires
    • H10W90/756—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires between a chip and a stacked lead frame, conducting package substrate or heat sink
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
    • Y10T29/00—Metal working
    • Y10T29/49—Method of mechanical manufacture
    • Y10T29/49002—Electrical device making
    • Y10T29/49117—Conductor or circuit manufacturing
    • Y10T29/49121—Beam lead frame or beam lead device

Landscapes

  • Lead Frames For Integrated Circuits (AREA)

Description

【発明の詳細な説明】 この発明は半導体装置、特にプラスチツクパツ
ケージ型半導体装置の組立に用いるリードフレー
ムに関するものである。
第１図は従来のリードフレームの一つの単位パ
ターンを示す図であり、中央に半導体素子を載置
するアイランド１を有し、その周囲には外方に延
びるリード２を複数個備えている。通常のリード
フレームはこのような単位パターンを複数個一枚
の金属板に備えている。一般にアイランド１の形
状は方形であり、その大きさは半導体素子の大き
さによつて決まるが現在半導体素子の種類が多種
多様なためアイランド１の大きさも多種多様であ
る。
第２図はこの従来のアイランド１及びリード２
のプレス金型による製作方法を示すもので、一般
にはアイランド１及びリード２を右から左に傾斜
する斜線で示すポンチ３で金属板を打ち抜いた後
左から右に傾斜する斜線で示すポンチ４によつて
再度金属板を打ち抜くというプレス加工を行なつ
て形成していた。もしアイランド１より大きなア
イランドが必要ならば、ポンチ３及び４はすべて
形状の異なるポンチに交換しなくてはならない。
又ポンチ３及び４は第３図に示す如くリードフレ
ームを製作するポンチの大部分を占めている。
従来はアイランド１の大きさが異なるとそれ相
応のプレス金型を製作してきたので１〜３千万円
の高価な費用及び長期の金型製作期間が必要だと
いう欠点があつた。又プレス金型の種類が多いた
め多くの金型を準備しておかなければ必要に即応
できず、費用がかかるばかりでなく、リードフレ
ーム製造の管理が煩雑になるという欠点があつ
た。またアイランドが大きくなると高価な金等の
メツキ面積が増大することにもなつていた。
この発明の目的は上述の従来の欠点を除去し、
しかもメツキ面積を減少させるリードフレームを
提供する事にある。
この発明の特徴は、半導体集積回路素子の組立
に使用するリードフレームにおいて、該リードフ
レームは半導体素子を載置するアイランド部と該
アイランド部近傍から外方に延長する複数のリー
ド部とを有し、前記アイランド部の周辺の側方に
は、前記リード部の先端とそれぞれ対向するよう
に凸部形状を有している半導体装置用リードフレ
ームである。
このリードフレームは、アイランドの大きさの
異なる種々のリードフレームに兼用でき、しかも
〓〓〓〓
メツキ面積を減少できるという利点をもたらす。
第４図は本発明の一実施例のリードフレームの
内部図であり、従来同様中央には半導体素子を載
置するアイランド５を有しその周辺にはリード７
を有しているが、アイランド５の周辺には櫛形の
凹凸が形成されている。このアイランド５は次の
ようにして製作される。即ち、金属板はまず従来
同様第２図のポンチ３で打ち抜かれるが、アイラ
ンド５はその大きさによりポンチ４だけ適宜交換
して第５図のポンチ６で打ち抜きしてプレス加工
される。この方法は大きいアイランドが必要な場
合、従来の新しいプレス金型を製作するのと異な
り、わずか数万円のポンチ６の製作費用及びポン
チ４の交換に要する１日の工数で所望の大きさの
アイランドが得られる。特に、従来のプレス金型
のうちポンチ３はその製作に１〜３千万円の費用
と３〜５カ月の期間を要し、本発明によればこの
ポンチ３は全てに使用できるので、高価な費用及
び遅い納期が不必要となる。
又一般に半導体素子をアイランド５に接着する
ため、アイランド５の全表面に金、銀等の貴金属
のメツキを施すが、本発明のリードフレームのア
イランド５の面積はアイランド５に四辺の凹部だ
け、従来のアイランドの面積より小さいのでそれ
だけメツキ費用が安いという利点がある。
【図面の簡単な説明】
第１図は従来のリードフレームの単位パターン
を示す部分平面図、第２図は従来のリードフレー
ムの加工方法を示すリードフレームとポンチの平
面図、第３図は従来リードフレームの外形図を示
す。第４図は本発明のリードフレームの単位パタ
ーンを示す部分平面図、第５図は本発明のリード
フレーム製作上必要なポンチ形状図を示す。 図中１……アイランド、２……リード、３，４
及び６……ポンチ、５……アイランドを示す。第
４図中破線は従来のリードフレームの内部図を示
す。 〓〓〓〓

Claims (1)

    【特許請求の範囲】
  1. １ 半導体集積回路素子の組立に使用するリード
    フレームにおいて、該リードフレームは半導体素
    子を載置するアイランド部と該アイランド部近傍
    から外方に延長する複数のリード部とを有し、前
    記アイランド部の周辺の側方には、前記リード部
    の先端とそれぞれ対向するように凸部形状を有し
    ていることを特徴とする半導体装置用リードフレ
    ーム。
JP14766277A 1977-12-07 1977-12-07 Lead frame for semiconductor Granted JPS5479563A (en)

Priority Applications (2)

Application Number Priority Date Filing Date Title
JP14766277A JPS5479563A (en) 1977-12-07 1977-12-07 Lead frame for semiconductor
US05/966,861 US4258381A (en) 1977-12-07 1978-12-06 Lead frame for a semiconductor device suitable for mass production

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP14766277A JPS5479563A (en) 1977-12-07 1977-12-07 Lead frame for semiconductor

Publications (2)

Publication Number Publication Date
JPS5479563A JPS5479563A (en) 1979-06-25
JPS6131627B2 true JPS6131627B2 (ja) 1986-07-21

Family

ID=15435424

Family Applications (1)

Application Number Title Priority Date Filing Date
JP14766277A Granted JPS5479563A (en) 1977-12-07 1977-12-07 Lead frame for semiconductor

Country Status (2)

Country Link
US (1) US4258381A (ja)
JP (1) JPS5479563A (ja)

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US4258381A (en) 1981-03-24

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