JPS6046074A - 電界効果トランジスタの製造方法 - Google Patents

電界効果トランジスタの製造方法

Info

Publication number
JPS6046074A
JPS6046074A JP58153166A JP15316683A JPS6046074A JP S6046074 A JPS6046074 A JP S6046074A JP 58153166 A JP58153166 A JP 58153166A JP 15316683 A JP15316683 A JP 15316683A JP S6046074 A JPS6046074 A JP S6046074A
Authority
JP
Japan
Prior art keywords
insulating film
semiconductor substrate
film
forming
metal film
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP58153166A
Other languages
English (en)
Japanese (ja)
Other versions
JPS6338869B2 (enrdf_load_stackoverflow
Inventor
Yutaka Etsuno
越野　裕
Tatsuo Akiyama
秋山　龍雄
Shunichi Kai
開　俊一
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Toshiba Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp filed Critical Toshiba Corp
Priority to JP58153166A priority Critical patent/JPS6046074A/ja
Publication of JPS6046074A publication Critical patent/JPS6046074A/ja
Priority to US06/843,833 priority patent/US4729966A/en
Publication of JPS6338869B2 publication Critical patent/JPS6338869B2/ja
Granted legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/01—Manufacture or treatment
    • H10D30/061—Manufacture or treatment of FETs having Schottky gates
    • H10D30/0612—Manufacture or treatment of FETs having Schottky gates of lateral single-gate Schottky FETs
    • H10D30/0616—Manufacture or treatment of FETs having Schottky gates of lateral single-gate Schottky FETs using processes wherein the final gate is made before the completion of the source and drain regions, e.g. gate-first processes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/28008—Making conductor-insulator-semiconductor electrodes
    • H01L21/28017—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon
    • H01L21/28026—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor
    • H01L21/28123—Lithography-related aspects, e.g. sub-lithography lengths; Isolation-related aspects, e.g. to solve problems arising at the crossing with the side of the device isolation; Planarisation aspects
    • H01L21/2815—Lithography-related aspects, e.g. sub-lithography lengths; Isolation-related aspects, e.g. to solve problems arising at the crossing with the side of the device isolation; Planarisation aspects part or whole of the electrode is a sidewall spacer or made by a similar technique, e.g. transformation under mask, plating
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/283—Deposition of conductive or insulating materials for electrodes conducting electric current
    • H01L21/285—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation
    • H01L21/28506—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers
    • H01L21/28575—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising AIIIBV compounds
    • H01L21/28587—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising AIIIBV compounds characterised by the sectional shape, e.g. T, inverted T

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Junction Field-Effect Transistors (AREA)
  • Electrodes Of Semiconductors (AREA)
JP58153166A 1983-08-24 1983-08-24 電界効果トランジスタの製造方法 Granted JPS6046074A (ja)

Priority Applications (2)

Application Number Priority Date Filing Date Title
JP58153166A JPS6046074A (ja) 1983-08-24 1983-08-24 電界効果トランジスタの製造方法
US06/843,833 US4729966A (en) 1983-08-24 1986-03-26 Process for manufacturing a Schottky FET device using metal sidewalls as gates

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP58153166A JPS6046074A (ja) 1983-08-24 1983-08-24 電界効果トランジスタの製造方法

Publications (2)

Publication Number Publication Date
JPS6046074A true JPS6046074A (ja) 1985-03-12
JPS6338869B2 JPS6338869B2 (enrdf_load_stackoverflow) 1988-08-02

Family

ID=15556489

Family Applications (1)

Application Number Title Priority Date Filing Date
JP58153166A Granted JPS6046074A (ja) 1983-08-24 1983-08-24 電界効果トランジスタの製造方法

Country Status (2)

Country Link
US (1) US4729966A (enrdf_load_stackoverflow)
JP (1) JPS6046074A (enrdf_load_stackoverflow)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS62156876A (ja) * 1985-12-28 1987-07-11 Matsushita Electronics Corp 半導体装置
JPS62243359A (ja) * 1986-04-15 1987-10-23 Matsushita Electric Ind Co Ltd 化合物半導体装置

Families Citing this family (25)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5187111A (en) * 1985-09-27 1993-02-16 Kabushiki Kaisha Toshiba Method of manufacturing Schottky barrier gate FET
JPS6346779A (ja) * 1986-08-15 1988-02-27 Nec Corp 半導体装置
JPH01109770A (ja) * 1987-10-22 1989-04-26 Mitsubishi Electric Corp 半導体装置の製造方法
US5143860A (en) * 1987-12-23 1992-09-01 Texas Instruments Incorporated High density EPROM fabricaiton method having sidewall floating gates
JP2685149B2 (ja) * 1988-04-11 1997-12-03 住友電気工業株式会社 電界効果トランジスタの製造方法
JPH0770721B2 (ja) * 1988-07-06 1995-07-31 株式会社東芝 半導体装置
US4945067A (en) * 1988-09-16 1990-07-31 Xerox Corporation Intra-gate offset high voltage thin film transistor with misalignment immunity and method of its fabrication
US5237192A (en) * 1988-10-12 1993-08-17 Mitsubishi Denki Kabushiki Kaisha MESFET semiconductor device having a T-shaped gate electrode
US5143857A (en) * 1988-11-07 1992-09-01 Triquint Semiconductor, Inc. Method of fabricating an electronic device with reduced susceptiblity to backgating effects
JP2553699B2 (ja) * 1989-04-12 1996-11-13 三菱電機株式会社 半導体装置の製造方法
EP0416141A1 (de) * 1989-09-04 1991-03-13 Siemens Aktiengesellschaft Verfahren zur Herstellung eines FET mit asymmetrisch angeordnetem Gate-Bereich
JPH0475351A (ja) * 1990-07-17 1992-03-10 Mitsubishi Electric Corp 化合物半導体装置の製造方法
FR2670606B1 (fr) * 1990-12-14 1993-02-12 Thomson Composants Microondes Procede de realisation de grilles submicroniques sur un dispositif semiconducteur.
EP0501275A3 (en) * 1991-03-01 1992-11-19 Motorola, Inc. Method of making symmetrical and asymmetrical mesfets
US5202272A (en) * 1991-03-25 1993-04-13 International Business Machines Corporation Field effect transistor formed with deep-submicron gate
CA2064146C (en) * 1991-03-28 1997-08-12 Hisashi Ariyoshi Schottky barrier diode and a method of manufacturing thereof
US5391510A (en) * 1992-02-28 1995-02-21 International Business Machines Corporation Formation of self-aligned metal gate FETs using a benignant removable gate material during high temperature steps
JPH08139103A (ja) * 1994-11-04 1996-05-31 Toyota Motor Corp 電界効果トランジスタおよびその製造方法
US6002148A (en) * 1995-06-30 1999-12-14 Motorola, Inc. Silicon carbide transistor and method
JPH09246285A (ja) * 1996-03-08 1997-09-19 Toshiba Corp 半導体装置及びその製造方法
US5923981A (en) * 1996-12-31 1999-07-13 Intel Corporation Cascading transistor gate and method for fabricating the same
US5864158A (en) * 1997-04-04 1999-01-26 Advanced Micro Devices, Inc. Trench-gated vertical CMOS device
US6610604B1 (en) 2002-02-05 2003-08-26 Chartered Semiconductor Manufacturing Ltd. Method of forming small transistor gates by using self-aligned reverse spacer as a hard mask
US7838371B2 (en) * 2006-11-06 2010-11-23 Nxp B.V. Method of manufacturing a FET gate
US20090218627A1 (en) * 2008-02-28 2009-09-03 International Business Machines Corporation Field effect device structure including self-aligned spacer shaped contact

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS57187967A (en) * 1981-05-14 1982-11-18 Nec Corp Manufacture of semiconductor device

Family Cites Families (13)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3969745A (en) * 1974-09-18 1976-07-13 Texas Instruments Incorporated Interconnection in multi element planar structures
US4194935A (en) * 1978-04-24 1980-03-25 Bell Telephone Laboratories, Incorporated Method of making high mobility multilayered heterojunction devices employing modulated doping
US4608589A (en) * 1980-07-08 1986-08-26 International Business Machines Corporation Self-aligned metal structure for integrated circuits
US4322883A (en) * 1980-07-08 1982-04-06 International Business Machines Corporation Self-aligned metal process for integrated injection logic integrated circuits
US4425379A (en) * 1981-02-11 1984-01-10 Fairchild Camera & Instrument Corporation Polycrystalline silicon Schottky diode array
US4389768A (en) * 1981-04-17 1983-06-28 International Business Machines Corporation Self-aligned process for fabricating gallium arsenide metal-semiconductor field effect transistors
US4409608A (en) * 1981-04-28 1983-10-11 The United States Of America As Represented By The Secretary Of The Navy Recessed interdigitated integrated capacitor
US4498093A (en) * 1981-09-14 1985-02-05 At&T Bell Laboratories High-power III-V semiconductor device
US4455738A (en) * 1981-12-24 1984-06-26 Texas Instruments Incorporated Self-aligned gate method for making MESFET semiconductor
EP0101752B1 (de) * 1982-08-25 1986-08-27 Ibm Deutschland Gmbh Umkehrprozess zum Herstellen von Chrommasken
US4521952A (en) * 1982-12-02 1985-06-11 International Business Machines Corporation Method of making integrated circuits using metal silicide contacts
US4532532A (en) * 1982-12-30 1985-07-30 International Business Machines Corporation Submicron conductor manufacturing
US4566941A (en) * 1983-05-10 1986-01-28 Kabushiki Kaisha Toshiba Reactive ion etching method

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS57187967A (en) * 1981-05-14 1982-11-18 Nec Corp Manufacture of semiconductor device

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS62156876A (ja) * 1985-12-28 1987-07-11 Matsushita Electronics Corp 半導体装置
JPS62243359A (ja) * 1986-04-15 1987-10-23 Matsushita Electric Ind Co Ltd 化合物半導体装置

Also Published As

Publication number Publication date
JPS6338869B2 (enrdf_load_stackoverflow) 1988-08-02
US4729966A (en) 1988-03-08

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