JPS57172737A - Forming method of throughhole - Google Patents

Forming method of throughhole

Info

Publication number
JPS57172737A
JPS57172737A JP5700481A JP5700481A JPS57172737A JP S57172737 A JPS57172737 A JP S57172737A JP 5700481 A JP5700481 A JP 5700481A JP 5700481 A JP5700481 A JP 5700481A JP S57172737 A JPS57172737 A JP S57172737A
Authority
JP
Japan
Prior art keywords
poly
insulating film
film
connecting holes
layer
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP5700481A
Other languages
Japanese (ja)
Inventor
Jun Kanamori
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Oki Electric Industry Co Ltd
Original Assignee
Oki Electric Industry Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Oki Electric Industry Co Ltd filed Critical Oki Electric Industry Co Ltd
Priority to JP5700481A priority Critical patent/JPS57172737A/en
Publication of JPS57172737A publication Critical patent/JPS57172737A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Drying Of Semiconductors (AREA)
  • Electrodes Of Semiconductors (AREA)

Abstract

PURPOSE:To form minute holes not to be polluted by impurities by a method wherein the P doped oxide film as an interlayer insulating film is covered with the poly Si mask to each the connecting holes. CONSTITUTION:A poly Si thin layer 32 is laminated on an insulating film 22 on a substrate provided with a diffused layer 12 and provided with a resist mask 42 to perforate said layer 32 without undercut. The resist 42 is removed and then the P doped oxide film 22 as the insulating film is etched by means of the parallel flat plate type unit using C2F6 and CHF3. With the resultant accumulation removed by means of reducing to ashes using O2 plasma, the required connecting holes 52 are formed. Through the constitution, the minute connecting holes 12 may be formed and the diffused layer 12 and others are not polluted by the Si film 22, because the poly Si film 22 is thin to be minutely perforated by means of the dry etching and said insulating film 22 is further dry-etched by the parallel flat plate type unit making use of the poly Si as the masking material.
JP5700481A 1981-04-17 1981-04-17 Forming method of throughhole Pending JPS57172737A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP5700481A JPS57172737A (en) 1981-04-17 1981-04-17 Forming method of throughhole

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP5700481A JPS57172737A (en) 1981-04-17 1981-04-17 Forming method of throughhole

Publications (1)

Publication Number Publication Date
JPS57172737A true JPS57172737A (en) 1982-10-23

Family

ID=13043316

Family Applications (1)

Application Number Title Priority Date Filing Date
JP5700481A Pending JPS57172737A (en) 1981-04-17 1981-04-17 Forming method of throughhole

Country Status (1)

Country Link
JP (1) JPS57172737A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS60133722A (en) * 1983-12-21 1985-07-16 Matsushita Electronics Corp Manufacture of integrated circuit
EP0991115A1 (en) * 1998-09-28 2000-04-05 STMicroelectronics S.r.l. Process for the definition of openings in a dielectric layer

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5421269A (en) * 1977-07-19 1979-02-17 Mitsubishi Electric Corp Manufacture for semiconductor mask
JPS54116882A (en) * 1978-03-02 1979-09-11 Nec Corp Manufacture of semiconductor device
JPS56277A (en) * 1979-06-12 1981-01-06 Chiyou Lsi Gijutsu Kenkyu Kumiai Forming method of metal layer pattern

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5421269A (en) * 1977-07-19 1979-02-17 Mitsubishi Electric Corp Manufacture for semiconductor mask
JPS54116882A (en) * 1978-03-02 1979-09-11 Nec Corp Manufacture of semiconductor device
JPS56277A (en) * 1979-06-12 1981-01-06 Chiyou Lsi Gijutsu Kenkyu Kumiai Forming method of metal layer pattern

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS60133722A (en) * 1983-12-21 1985-07-16 Matsushita Electronics Corp Manufacture of integrated circuit
EP0991115A1 (en) * 1998-09-28 2000-04-05 STMicroelectronics S.r.l. Process for the definition of openings in a dielectric layer
US6313040B1 (en) 1998-09-28 2001-11-06 Stmicroelectronics S.R.L. Process for the definition of openings in a dielectric layer

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