JPS57111032A - Forming method for pattern - Google Patents

Forming method for pattern

Info

Publication number
JPS57111032A
JPS57111032A JP55189024A JP18902480A JPS57111032A JP S57111032 A JPS57111032 A JP S57111032A JP 55189024 A JP55189024 A JP 55189024A JP 18902480 A JP18902480 A JP 18902480A JP S57111032 A JPS57111032 A JP S57111032A
Authority
JP
Japan
Prior art keywords
layer
oxidizing
pattern
oxide layer
patterned
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP55189024A
Other languages
Japanese (ja)
Other versions
JPS634700B2 (en
Inventor
Kazuo Hirata
Masatoshi Oda
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Nippon Telegraph and Telephone Corp
Original Assignee
Nippon Telegraph and Telephone Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Nippon Telegraph and Telephone Corp filed Critical Nippon Telegraph and Telephone Corp
Priority to JP55189024A priority Critical patent/JPS57111032A/en
Priority to NLAANVRAGE8105661,A priority patent/NL188432C/en
Priority to US06/331,612 priority patent/US4460413A/en
Priority to FR8123625A priority patent/FR2497403B1/en
Priority to GB8138219A priority patent/GB2092373B/en
Priority to DE19813151915 priority patent/DE3151915A1/en
Priority to CA000393192A priority patent/CA1186600A/en
Publication of JPS57111032A publication Critical patent/JPS57111032A/en
Publication of JPS634700B2 publication Critical patent/JPS634700B2/ja
Granted legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/28008—Making conductor-insulator-semiconductor electrodes
    • H01L21/28017—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon
    • H01L21/28026—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor
    • H01L21/28123—Lithography-related aspects, e.g. sub-lithography lengths; Isolation-related aspects, e.g. to solve problems arising at the crossing with the side of the device isolation; Planarisation aspects
    • H01L21/28132—Lithography-related aspects, e.g. sub-lithography lengths; Isolation-related aspects, e.g. to solve problems arising at the crossing with the side of the device isolation; Planarisation aspects conducting part of electrode is difined by a sidewall spacer or a similar technique, e.g. oxidation under mask, plating
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Drying Of Semiconductors (AREA)
  • Formation Of Insulating Films (AREA)

Abstract

PURPOSE:To form an oxide layer with a desired minute pattern by oxidizing an oxidizing layer being patterned, shaping the oxide layer on a side surface and removing the oxidizing layer. CONSTITUTION:The oxidizing layer 17 in Al, etc. formed onto a Si substrate 11 is patterned by using a photo-resist layer 16, the oxide layer 18 of Al2O3, etc. is shaped onto the surface in the thickness of approximately 0.02-0.4mum through oxidation treatment such as immersion in hot water, the remaining Al17 is removed through dry etching treatment employing a CCl4 gas, and the minute pattern consisting of Al2O318 is formed. Accordingly, the desired pattern in submicron order can be shaped on the substrate.
JP55189024A 1980-12-26 1980-12-26 Forming method for pattern Granted JPS57111032A (en)

Priority Applications (7)

Application Number Priority Date Filing Date Title
JP55189024A JPS57111032A (en) 1980-12-26 1980-12-26 Forming method for pattern
NLAANVRAGE8105661,A NL188432C (en) 1980-12-26 1981-12-16 METHOD FOR MANUFACTURING A MOSFET
US06/331,612 US4460413A (en) 1980-12-26 1981-12-17 Method of patterning device regions by oxidizing patterned aluminum layer
FR8123625A FR2497403B1 (en) 1980-12-26 1981-12-17 PROCESS FOR FORMING EXTREMELY THIN NETWORKS IN PARTICULAR FOR MANUFACTURING TRANSISTORS
GB8138219A GB2092373B (en) 1980-12-26 1981-12-18 A method of forming patterns
DE19813151915 DE3151915A1 (en) 1980-12-26 1981-12-23 METHOD FOR FORMING PATTERNS OR TEMPLATES
CA000393192A CA1186600A (en) 1980-12-26 1981-12-24 Method of forming patterns

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP55189024A JPS57111032A (en) 1980-12-26 1980-12-26 Forming method for pattern

Publications (2)

Publication Number Publication Date
JPS57111032A true JPS57111032A (en) 1982-07-10
JPS634700B2 JPS634700B2 (en) 1988-01-30

Family

ID=16234019

Family Applications (1)

Application Number Title Priority Date Filing Date
JP55189024A Granted JPS57111032A (en) 1980-12-26 1980-12-26 Forming method for pattern

Country Status (1)

Country Link
JP (1) JPS57111032A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5957450A (en) * 1982-09-27 1984-04-03 Nec Corp Isolating method for element of semiconductor device

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5212546A (en) * 1975-07-21 1977-01-31 Tektronix Inc Parallel phase amplifier
JPS55163863A (en) * 1979-06-07 1980-12-20 Matsushita Electric Ind Co Ltd Formation of wiring pattern

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5212546A (en) * 1975-07-21 1977-01-31 Tektronix Inc Parallel phase amplifier
JPS55163863A (en) * 1979-06-07 1980-12-20 Matsushita Electric Ind Co Ltd Formation of wiring pattern

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5957450A (en) * 1982-09-27 1984-04-03 Nec Corp Isolating method for element of semiconductor device

Also Published As

Publication number Publication date
JPS634700B2 (en) 1988-01-30

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