JPS5713740A - Forming method for conductor pattern - Google Patents

Forming method for conductor pattern

Info

Publication number
JPS5713740A
JPS5713740A JP8959380A JP8959380A JPS5713740A JP S5713740 A JPS5713740 A JP S5713740A JP 8959380 A JP8959380 A JP 8959380A JP 8959380 A JP8959380 A JP 8959380A JP S5713740 A JPS5713740 A JP S5713740A
Authority
JP
Japan
Prior art keywords
layer
resist layer
retained
conductor
forming method
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP8959380A
Other languages
Japanese (ja)
Inventor
Shuji Watanabe
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP8959380A priority Critical patent/JPS5713740A/en
Publication of JPS5713740A publication Critical patent/JPS5713740A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Electrodes Of Semiconductors (AREA)
  • Weting (AREA)

Abstract

PURPOSE:To facilitate the removal of a resist layer by patterning the negative resist layer in the prescribed shape to become without contact with a metallic electrode and forming a conductor layer having the resist layer thereon. CONSTITUTION:A metallic electrode 11, an SiO2 film 12 and a negative resist layer 13 are formed on the surface of a substrate 19, a phtosensitive part of the layer 13 is retained with photomask, and the retained layer 13 is patterned larger than the pattern of the electrode 11. Then, conductor layers 14a, 14b are adhered above the substrate 10, are then dipped in an exfoliating solution, and the layer 13 is removed together with unnecessary layer 14b adhered on the layer 13. In this manner, the resist layer can be readily exfoliated from the film 12, and the conductor layer can not be retained unnecessarily.
JP8959380A 1980-06-30 1980-06-30 Forming method for conductor pattern Pending JPS5713740A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP8959380A JPS5713740A (en) 1980-06-30 1980-06-30 Forming method for conductor pattern

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP8959380A JPS5713740A (en) 1980-06-30 1980-06-30 Forming method for conductor pattern

Publications (1)

Publication Number Publication Date
JPS5713740A true JPS5713740A (en) 1982-01-23

Family

ID=13975071

Family Applications (1)

Application Number Title Priority Date Filing Date
JP8959380A Pending JPS5713740A (en) 1980-06-30 1980-06-30 Forming method for conductor pattern

Country Status (1)

Country Link
JP (1) JPS5713740A (en)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS58117867U (en) * 1982-02-03 1983-08-11 ダイワ精工株式会社 Fishing reel buckle crash prevention device
JPS5910227A (en) * 1982-07-09 1984-01-19 Nec Corp Semiconductor device
JPH04278531A (en) * 1991-03-06 1992-10-05 Fujitsu Ltd Manufacture of semiconductor device having an uneven sectional shape

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS58117867U (en) * 1982-02-03 1983-08-11 ダイワ精工株式会社 Fishing reel buckle crash prevention device
JPH0115343Y2 (en) * 1982-02-03 1989-05-09
JPS5910227A (en) * 1982-07-09 1984-01-19 Nec Corp Semiconductor device
JPH0141016B2 (en) * 1982-07-09 1989-09-01 Nippon Electric Co
JPH04278531A (en) * 1991-03-06 1992-10-05 Fujitsu Ltd Manufacture of semiconductor device having an uneven sectional shape

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