JPS5568674A - Fabrication of charge coupled device - Google Patents

Fabrication of charge coupled device

Info

Publication number
JPS5568674A
JPS5568674A JP14309178A JP14309178A JPS5568674A JP S5568674 A JPS5568674 A JP S5568674A JP 14309178 A JP14309178 A JP 14309178A JP 14309178 A JP14309178 A JP 14309178A JP S5568674 A JPS5568674 A JP S5568674A
Authority
JP
Japan
Prior art keywords
layer
film
pattern
coated
eaves
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP14309178A
Other languages
Japanese (ja)
Other versions
JPS6057229B2 (en
Inventor
Junji Sakurai
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP53143091A priority Critical patent/JPS6057229B2/en
Publication of JPS5568674A publication Critical patent/JPS5568674A/en
Publication of JPS6057229B2 publication Critical patent/JPS6057229B2/en
Expired legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268

Abstract

PURPOSE:To obtain electrode train of infinitesimal interval in a charge coupled device by providing a resist pattern having eaves, on a conductivity layer becoming electrodes when forming the electrodes of the charge coupled device and exposing and etching the conductivity layer under the eaves when coating metallic thin film on the entire surface thereof. CONSTITUTION:A gate SiO2 film 2 is coated on a silicon substrate 1, a polycrystalline silicon conductivity layer 10 is vapor grown thereon, and a positive resist film 11 is coated thereon. Then, light is exposed on the film 11 in sufficient exposure time and illumination thereof by using a photomask having a minimum pattern width formed possibly, the film 11 is then developed to thereby form a resist pattern 11' having a pattern width of approx. 3mum and eaves 12 of approx. 2,000Angstrom is formed at the periphery thereof. When an aluminum thin layer 13 is then coated on the entire surface, the pattern 11' is separated from the layer 10 so that the layer is not coated underneath the defects 12. Accordingly, it is plasma etched to thereby remove the eaves portion of the layer 10 to thus retain the layer 10 as electrode train but to remove the pattern 11'.
JP53143091A 1978-11-20 1978-11-20 Method of manufacturing a charge-coupled device Expired JPS6057229B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP53143091A JPS6057229B2 (en) 1978-11-20 1978-11-20 Method of manufacturing a charge-coupled device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP53143091A JPS6057229B2 (en) 1978-11-20 1978-11-20 Method of manufacturing a charge-coupled device

Publications (2)

Publication Number Publication Date
JPS5568674A true JPS5568674A (en) 1980-05-23
JPS6057229B2 JPS6057229B2 (en) 1985-12-13

Family

ID=15330694

Family Applications (1)

Application Number Title Priority Date Filing Date
JP53143091A Expired JPS6057229B2 (en) 1978-11-20 1978-11-20 Method of manufacturing a charge-coupled device

Country Status (1)

Country Link
JP (1) JPS6057229B2 (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5750465A (en) * 1980-09-11 1982-03-24 Fujitsu Ltd Semiconductor memory device
JPS58142526A (en) * 1982-02-19 1983-08-24 Comput Basic Mach Technol Res Assoc Patterning method of thin film

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5750465A (en) * 1980-09-11 1982-03-24 Fujitsu Ltd Semiconductor memory device
JPS58142526A (en) * 1982-02-19 1983-08-24 Comput Basic Mach Technol Res Assoc Patterning method of thin film

Also Published As

Publication number Publication date
JPS6057229B2 (en) 1985-12-13

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