JPS5681954A - Manufacture of semiconductor ic - Google Patents

Manufacture of semiconductor ic

Info

Publication number
JPS5681954A
JPS5681954A JP15949179A JP15949179A JPS5681954A JP S5681954 A JPS5681954 A JP S5681954A JP 15949179 A JP15949179 A JP 15949179A JP 15949179 A JP15949179 A JP 15949179A JP S5681954 A JPS5681954 A JP S5681954A
Authority
JP
Japan
Prior art keywords
films
wiring
etching
pattern
inverted
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP15949179A
Other languages
Japanese (ja)
Inventor
Minoru Taguchi
Yoshitaka Sasaki
Hajime Sasaki
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Toshiba Corp
Tokyo Shibaura Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp, Tokyo Shibaura Electric Co Ltd filed Critical Toshiba Corp
Priority to JP15949179A priority Critical patent/JPS5681954A/en
Publication of JPS5681954A publication Critical patent/JPS5681954A/en
Pending legal-status Critical Current

Links

Landscapes

  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Electrodes Of Semiconductors (AREA)

Abstract

PURPOSE:To obtain a highly precise and reliable wiring for the subject semiconductor IC by a method wherein a metal silicide is evaporated and lifted off using the mask having an inverted tapering section. CONSTITUTION:An aparture is provided on the SiO2 8 and Si3N4 9 on an elementformed subdtrate, and a PSG11 and CVD-SiO2 12 films are laminated. When the films 11 and 12 are etched by providing a resist mask 13, an inverted tapered type pattern 14 is selectively formed utilizing the difference of etching speed. The resist mask is removed and an MoSi2 151 and 152 films are deposited. After that, when the pattern 14 is removed by etching using NH4F, electrodes 16-18 are completed. As the metal silicide having an excellent etchingproof and heatproof property is used for the electrode material, there exists no partial removal and change in quality of the electrode wiring when the inverted tapering pattern 14 is removed by etching, and the rising of the wiring caused by heat treatment is prevented and a highly precise and reliable wiring can be obtained.
JP15949179A 1979-12-08 1979-12-08 Manufacture of semiconductor ic Pending JPS5681954A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP15949179A JPS5681954A (en) 1979-12-08 1979-12-08 Manufacture of semiconductor ic

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP15949179A JPS5681954A (en) 1979-12-08 1979-12-08 Manufacture of semiconductor ic

Publications (1)

Publication Number Publication Date
JPS5681954A true JPS5681954A (en) 1981-07-04

Family

ID=15694919

Family Applications (1)

Application Number Title Priority Date Filing Date
JP15949179A Pending JPS5681954A (en) 1979-12-08 1979-12-08 Manufacture of semiconductor ic

Country Status (1)

Country Link
JP (1) JPS5681954A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2008016061A1 (en) 2006-08-02 2008-02-07 Asahi Glass Co., Ltd. Electronic circuit device and method for fabricating the same
US7790358B2 (en) 2003-11-11 2010-09-07 Asahi Glass Company, Limited Pattern formation method, electronic circuit manufactured by the same, and electronic device using the same

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7790358B2 (en) 2003-11-11 2010-09-07 Asahi Glass Company, Limited Pattern formation method, electronic circuit manufactured by the same, and electronic device using the same
WO2008016061A1 (en) 2006-08-02 2008-02-07 Asahi Glass Co., Ltd. Electronic circuit device and method for fabricating the same
US8418359B2 (en) 2006-08-02 2013-04-16 Asahi Glass Company, Limited Method for manufacturing circuit pattern-provided substrate

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