JPS54105482A - Manufacture of semiconductor - Google Patents

Manufacture of semiconductor

Info

Publication number
JPS54105482A
JPS54105482A JP1284078A JP1284078A JPS54105482A JP S54105482 A JPS54105482 A JP S54105482A JP 1284078 A JP1284078 A JP 1284078A JP 1284078 A JP1284078 A JP 1284078A JP S54105482 A JPS54105482 A JP S54105482A
Authority
JP
Japan
Prior art keywords
film
layer
poly
gas
phosphorus
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP1284078A
Other languages
Japanese (ja)
Inventor
Masahiro Hatanaka
Tsutomu Yoshihara
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Mitsubishi Electric Corp
Original Assignee
Mitsubishi Electric Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Mitsubishi Electric Corp filed Critical Mitsubishi Electric Corp
Priority to JP1284078A priority Critical patent/JPS54105482A/en
Publication of JPS54105482A publication Critical patent/JPS54105482A/en
Pending legal-status Critical Current

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Abstract

PURPOSE: To increase a degree of integration through self-matching between a source-drain layer and its wiring using poly-Si.
CONSTITUTION: On field oxidized film 9 and gate oxidized film 10 on P-type Si substrate 8, Al film 11 is formed; film 11 is plasma-etched by CCl4 gas using resist mask 12, and film 10 is by CF4 gas. After phosphorus-added poly-Si 13 is deposited, Al 11 is selectively etched by CF4 gas plasma and heating in N2 causes phosphorus diffusion from film 13 to form source-drain 14, thereby changing film 13 into an ohmic-contact electrode wiring layer. Next, thermally-oxidized film 15 is formed on the surface of poly-Si 13 and phosphorus-added poly-Si 16 is stacked; and layer 16 is selectively etched by using resist mask 17 to make gate electrode 16 and the mask is removed, thereby obtaining a MOSFET. In this constitution, a process of forming a connection window is omitted, the degree of integration can be increased, and no punching through of Al occurs because of the interposition of layer 13.
COPYRIGHT: (C)1979,JPO&Japio
JP1284078A 1978-02-06 1978-02-06 Manufacture of semiconductor Pending JPS54105482A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP1284078A JPS54105482A (en) 1978-02-06 1978-02-06 Manufacture of semiconductor

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP1284078A JPS54105482A (en) 1978-02-06 1978-02-06 Manufacture of semiconductor

Publications (1)

Publication Number Publication Date
JPS54105482A true JPS54105482A (en) 1979-08-18

Family

ID=11816571

Family Applications (1)

Application Number Title Priority Date Filing Date
JP1284078A Pending JPS54105482A (en) 1978-02-06 1978-02-06 Manufacture of semiconductor

Country Status (1)

Country Link
JP (1) JPS54105482A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS603158A (en) * 1983-06-06 1985-01-09 インタ−ナショナル　ビジネス　マシ−ンズ　コ−ポレ−ション Method of forming field effect transistor

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS603158A (en) * 1983-06-06 1985-01-09 インタ−ナショナル　ビジネス　マシ−ンズ　コ−ポレ−ション Method of forming field effect transistor
JPH0523056B2 (en) * 1983-06-06 1993-03-31 Intaanashonaru Bijinesu Mashiinzu Corp

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