JPS5447489A - Production of mos semiconductor device - Google Patents

Production of mos semiconductor device

Info

Publication number
JPS5447489A
JPS5447489A JP11270677A JP11270677A JPS5447489A JP S5447489 A JPS5447489 A JP S5447489A JP 11270677 A JP11270677 A JP 11270677A JP 11270677 A JP11270677 A JP 11270677A JP S5447489 A JPS5447489 A JP S5447489A
Authority
JP
Japan
Prior art keywords
poly
gate
implanted
ions
self
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP11270677A
Other languages
Japanese (ja)
Inventor
Yasunobu Osa
Yukio Tanigaki
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Ltd
Original Assignee
Hitachi Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Ltd filed Critical Hitachi Ltd
Priority to JP11270677A priority Critical patent/JPS5447489A/en
Publication of JPS5447489A publication Critical patent/JPS5447489A/en
Pending legal-status Critical Current

Links

Abstract

PURPOSE: To minimize spacing by forming poly-Si gates of eaves form or a negative grade and providing source and drain electrodes through self-alignment.
CONSTITUTION: A field oxide film 2 and a gate oxide film 3 are provided on an n type Si substrate 1 and poly-si 4 is deposited. The side faces of the poly-Si gate 4a are deeply removed (d) by gas plasma etching through a resist mask 5. After p ions are implanted, the film 3 is etched away and Al is evaportated, then the conductor layers 6a, 6b are isolatedly formed because of the eaves part. Next, the reist is lifted off to remove the layer 6b, and p ions are supplementarily implanted and annealed, after which an Al layer 8 is formed. In this way the gate electrodes as well as source and drain electrodes may be formed at the shortest distance in a self-alignment manner
COPYRIGHT: (C)1979,JPO&Japio
JP11270677A 1977-09-21 1977-09-21 Production of mos semiconductor device Pending JPS5447489A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP11270677A JPS5447489A (en) 1977-09-21 1977-09-21 Production of mos semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP11270677A JPS5447489A (en) 1977-09-21 1977-09-21 Production of mos semiconductor device

Publications (1)

Publication Number Publication Date
JPS5447489A true JPS5447489A (en) 1979-04-14

Family

ID=14593447

Family Applications (1)

Application Number Title Priority Date Filing Date
JP11270677A Pending JPS5447489A (en) 1977-09-21 1977-09-21 Production of mos semiconductor device

Country Status (1)

Country Link
JP (1) JPS5447489A (en)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS603158A (en) * 1983-06-06 1985-01-09 インタ−ナショナル　ビジネス　マシ−ンズ　コ−ポレ−ション Method of forming field effect transistor
US4837181A (en) * 1987-06-11 1989-06-06 Sgs-Thomson Microelectronics S.R.L. ROM memory programming procedure using MOS technology with thin gate oxide and junctions
US5115290A (en) * 1989-09-06 1992-05-19 Kabushiki Kaisha Toshiba Mos type semiconductor device and method for manufacturing the same

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS603158A (en) * 1983-06-06 1985-01-09 インタ−ナショナル　ビジネス　マシ−ンズ　コ−ポレ−ション Method of forming field effect transistor
JPH0523056B2 (en) * 1983-06-06 1993-03-31 Intaanashonaru Bijinesu Mashiinzu Corp
US4837181A (en) * 1987-06-11 1989-06-06 Sgs-Thomson Microelectronics S.R.L. ROM memory programming procedure using MOS technology with thin gate oxide and junctions
US5115290A (en) * 1989-09-06 1992-05-19 Kabushiki Kaisha Toshiba Mos type semiconductor device and method for manufacturing the same

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