JPS56158447A - Semiconductor integrated circuit and its manufacture - Google Patents

Semiconductor integrated circuit and its manufacture

Info

Publication number
JPS56158447A
JPS56158447A JP6325480A JP6325480A JPS56158447A JP S56158447 A JPS56158447 A JP S56158447A JP 6325480 A JP6325480 A JP 6325480A JP 6325480 A JP6325480 A JP 6325480A JP S56158447 A JPS56158447 A JP S56158447A
Authority
JP
Japan
Prior art keywords
layers
films
polycrystalline
type
bsg
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP6325480A
Other languages
Japanese (ja)
Inventor
Tadanaka Yoneda
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Panasonic Holdings Corp
Original Assignee
Matsushita Electric Industrial Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Matsushita Electric Industrial Co Ltd filed Critical Matsushita Electric Industrial Co Ltd
Priority to JP6325480A priority Critical patent/JPS56158447A/en
Publication of JPS56158447A publication Critical patent/JPS56158447A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Local Oxidation Of Silicon (AREA)
  • Element Separation (AREA)

Abstract

PURPOSE:To enhance withstand voltage of the semiconductor integrated circuit and threshold voltage of a parasitic MOS by a method wherein BSG films are provided selectively on a P type substrate, epitaxial layers are accumulated thereon to form polycrystalline Si layers, the half of the thickness thereof are etched to form grooves, and field oxide films having small occupying area are formed by wet oxidation. CONSTITUTION:The BSG layers 21 are provided selectively on the P type Si substrate 20, and when the P type epitaxial layers 22 are accumulated thereon, the polycrystalline Si layers 23 are formed on the BSG layers. SiO2 films 24 and Si3N4 films 25 are accumulated thereon, and openings are formed in the films 25, 24 applying a resist mask 26. Sputter etching is performed using CF4 gas to remove the half thickness of the polycrystalline Si layers 23. Ar ions are implanted to convert the polycrystalline Si layers 23 into polycrystalline Si films 24' having high speed of oxidation. The resist mask 26 is removed, and wet oxidation is performed to form field oxide films 27. At this time, B ions are diffused from the BSG films 21 to form P<+> type polycrystalline Si layers 31 and P<+> type layers 32. The films 25 are removed, and the insulated gate type FET is formed. By this constitution, the field oxide films having a small occupying area can be obtained, and threshold voltage can be enhanced because the directly under parts thereof are polycrystalline layers.
JP6325480A 1980-05-12 1980-05-12 Semiconductor integrated circuit and its manufacture Pending JPS56158447A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP6325480A JPS56158447A (en) 1980-05-12 1980-05-12 Semiconductor integrated circuit and its manufacture

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP6325480A JPS56158447A (en) 1980-05-12 1980-05-12 Semiconductor integrated circuit and its manufacture

Publications (1)

Publication Number Publication Date
JPS56158447A true JPS56158447A (en) 1981-12-07

Family

ID=13223931

Family Applications (1)

Application Number Title Priority Date Filing Date
JP6325480A Pending JPS56158447A (en) 1980-05-12 1980-05-12 Semiconductor integrated circuit and its manufacture

Country Status (1)

Country Link
JP (1) JPS56158447A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5141884A (en) * 1990-08-18 1992-08-25 Samsung Electronics Co., Ltd. Isolation method of semiconductor device

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5141884A (en) * 1990-08-18 1992-08-25 Samsung Electronics Co., Ltd. Isolation method of semiconductor device

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