JPS5454577A - Material working method with photo resist - Google Patents

Material working method with photo resist

Info

Publication number
JPS5454577A
JPS5454577A JP12093777A JP12093777A JPS5454577A JP S5454577 A JPS5454577 A JP S5454577A JP 12093777 A JP12093777 A JP 12093777A JP 12093777 A JP12093777 A JP 12093777A JP S5454577 A JPS5454577 A JP S5454577A
Authority
JP
Japan
Prior art keywords
working
film
mask
etched
resist
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP12093777A
Other languages
Japanese (ja)
Other versions
JPS6238852B2 (en
Inventor
Yoshiaki Kamigaki
Nobuo Hasegawa
Kiyoo Ito
Yoshifumi Kawamoto
Tetsukazu Hashimoto
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Ltd
Original Assignee
Hitachi Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Ltd filed Critical Hitachi Ltd
Priority to JP12093777A priority Critical patent/JPS5454577A/en
Publication of JPS5454577A publication Critical patent/JPS5454577A/en
Publication of JPS6238852B2 publication Critical patent/JPS6238852B2/ja
Granted legal-status Critical Current

Links

Landscapes

  • Weting (AREA)
  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
  • Exposure Of Semiconductors, Excluding Electron Or Ion Beam Exposure (AREA)

Abstract

PURPOSE: To perform fine working by softening the photo resist film having been made in eaves form to allow the same to be contacted to the material being worked and working the material being worked at least twice in a self-alignment manner.
CONSTITUTION: An oxide film 2, phosphorus-doped poly-Si 3 and an oxide thin film 4 are laminated on a p type Si substrate 1 and a resist mask 5 is made. When etching is performed by keeping a NH2F/HF solution of 6:1 at 20°C, then side etching size and variations in shape may be made sufficiently small and the fil m 4 is etched. Following to this, the substrate is treated for 10 minutes at 140°C to soften the resist 5, after which the film 3 is plasma-etched to remove the mask 5. Next, n+ layers 6-1, 6-2 are provided by implanting As and the film 3 is plasma- etched through the mask 4, after which As is driven to provide n layers 7-1, 7-2, whereby a MOSFET is created. Then, working more than twice in a self-alignment manner becomes possible with one kind of mask and fine working may be formed with good controllability of working and working shape
COPYRIGHT: (C)1979,JPO&Japio
JP12093777A 1977-10-11 1977-10-11 Material working method with photo resist Granted JPS5454577A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP12093777A JPS5454577A (en) 1977-10-11 1977-10-11 Material working method with photo resist

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP12093777A JPS5454577A (en) 1977-10-11 1977-10-11 Material working method with photo resist

Publications (2)

Publication Number Publication Date
JPS5454577A true JPS5454577A (en) 1979-04-28
JPS6238852B2 JPS6238852B2 (en) 1987-08-20

Family

ID=14798649

Family Applications (1)

Application Number Title Priority Date Filing Date
JP12093777A Granted JPS5454577A (en) 1977-10-11 1977-10-11 Material working method with photo resist

Country Status (1)

Country Link
JP (1) JPS5454577A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4818715A (en) * 1987-07-09 1989-04-04 Industrial Technology Research Institute Method of fabricating a LDDFET with self-aligned silicide

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS50134579A (en) * 1974-04-13 1975-10-24
JPS5235980A (en) * 1975-09-16 1977-03-18 Hitachi Ltd Manufacturing method of semiconductor device

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS50134579A (en) * 1974-04-13 1975-10-24
JPS5235980A (en) * 1975-09-16 1977-03-18 Hitachi Ltd Manufacturing method of semiconductor device

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4818715A (en) * 1987-07-09 1989-04-04 Industrial Technology Research Institute Method of fabricating a LDDFET with self-aligned silicide

Also Published As

Publication number Publication date
JPS6238852B2 (en) 1987-08-20

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