JPS6238852B2 - - Google Patents
Info
- Publication number
- JPS6238852B2 JPS6238852B2 JP52120937A JP12093777A JPS6238852B2 JP S6238852 B2 JPS6238852 B2 JP S6238852B2 JP 52120937 A JP52120937 A JP 52120937A JP 12093777 A JP12093777 A JP 12093777A JP S6238852 B2 JPS6238852 B2 JP S6238852B2
- Authority
- JP
- Japan
- Prior art keywords
- film
- mask
- photoresist
- processing
- processed
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
- 239000000463 material Substances 0.000 claims description 29
- 238000005530 etching Methods 0.000 claims description 15
- 239000000758 substrate Substances 0.000 claims description 7
- 238000003672 processing method Methods 0.000 claims description 6
- 238000010030 laminating Methods 0.000 claims 1
- 229920002120 photoresistant polymer Polymers 0.000 description 38
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 17
- 238000000034 method Methods 0.000 description 11
- 239000004065 semiconductor Substances 0.000 description 11
- 238000002513 implantation Methods 0.000 description 6
- 230000003647 oxidation Effects 0.000 description 5
- 238000007254 oxidation reaction Methods 0.000 description 5
- 238000009792 diffusion process Methods 0.000 description 4
- 238000004519 manufacturing process Methods 0.000 description 4
- 238000001020 plasma etching Methods 0.000 description 4
- 229910052785 arsenic Inorganic materials 0.000 description 3
- RQNWIZPPADIBDY-UHFFFAOYSA-N arsenic atom Chemical compound [As] RQNWIZPPADIBDY-UHFFFAOYSA-N 0.000 description 3
- 239000007943 implant Substances 0.000 description 3
- 229920005989 resin Polymers 0.000 description 3
- 239000011347 resin Substances 0.000 description 3
- DDFHBQSCUXNBSA-UHFFFAOYSA-N 5-(5-carboxythiophen-2-yl)thiophene-2-carboxylic acid Chemical compound S1C(C(=O)O)=CC=C1C1=CC=C(C(O)=O)S1 DDFHBQSCUXNBSA-UHFFFAOYSA-N 0.000 description 2
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 2
- 229910004298 SiO 2 Inorganic materials 0.000 description 2
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 2
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 2
- 238000005229 chemical vapour deposition Methods 0.000 description 2
- KRHYYFGTRYWZRS-UHFFFAOYSA-N hydrofluoric acid Substances F KRHYYFGTRYWZRS-UHFFFAOYSA-N 0.000 description 2
- 239000012535 impurity Substances 0.000 description 2
- QPJSUIGXIBEQAC-UHFFFAOYSA-N n-(2,4-dichloro-5-propan-2-yloxyphenyl)acetamide Chemical compound CC(C)OC1=CC(NC(C)=O)=C(Cl)C=C1Cl QPJSUIGXIBEQAC-UHFFFAOYSA-N 0.000 description 2
- 229910052698 phosphorus Inorganic materials 0.000 description 2
- 239000011574 phosphorus Substances 0.000 description 2
- 238000000206 photolithography Methods 0.000 description 2
- 229910052710 silicon Inorganic materials 0.000 description 2
- 239000010703 silicon Substances 0.000 description 2
- 229910052814 silicon oxide Inorganic materials 0.000 description 2
- 238000003491 array Methods 0.000 description 1
- 230000015556 catabolic process Effects 0.000 description 1
- 230000006866 deterioration Effects 0.000 description 1
- 238000010894 electron beam technology Methods 0.000 description 1
- 238000010438 heat treatment Methods 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 238000002955 isolation Methods 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 230000001590 oxidative effect Effects 0.000 description 1
- 230000002250 progressing effect Effects 0.000 description 1
- 230000005855 radiation Effects 0.000 description 1
- 238000009279 wet oxidation reaction Methods 0.000 description 1
Landscapes
- Weting (AREA)
- Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
- Exposure Of Semiconductors, Excluding Electron Or Ion Beam Exposure (AREA)
Description
【発明の詳細な説明】
(1) 発明の利用分野
本発明は、フオトレジストによる材料加工法に
関し、とくに自己整合的な加工法を提供し、微細
加工の点で有効な加工法に関するものである。[Detailed Description of the Invention] (1) Field of Application of the Invention The present invention relates to a material processing method using photoresist, and particularly to a processing method that provides a self-aligning processing method and is effective in terms of microfabrication. .
(2) 従来技術
従来、写真蝕刻法により被加工材料を２回以上
加工する際、フオトマスクを２種類以上準備しな
くてはならなかつた。そのため、１回目の加工と
２回目の加工との間には、マスク合わせ余裕が必
要となり、その分加工精度の劣下を考慮しておく
必要があつた。また、サイド・エツチング法など
も用いられてはいたが、加工寸法の面で、いま一
歩満足できるものではなかつた。(2) Prior Art Conventionally, when processing a workpiece material more than once by photolithography, it was necessary to prepare two or more types of photomasks. Therefore, a margin for mask alignment is required between the first processing and the second processing, and it is necessary to take into account the deterioration in processing accuracy. Also, although side etching methods have been used, they have not been completely satisfactory in terms of processing dimensions.
(3) 発明の目的
したがつて本発明は、写真蝕刻法により被加工
材料を加工する際、自戸整合的な方法をとり、し
かも加工性の面で、その制御性さらに加工形状の
十分に満足のできるフオトレジスト加工法を提供
するものである。(3) Purpose of the invention Therefore, the present invention uses a self-consistent method when processing a workpiece material by photolithography, and also improves controllability and sufficient processing shape in terms of processability. The present invention provides a satisfactory photoresist processing method.
(4) 発明の総括説明
一種類のフオトマスクを用い、フオトレジスト
膜下に第２の加工マスク材を形成し、パターニン
グされたフオトレジスト膜をマスクにして第２の
加工マスク材を所望の寸法だけオーバ・エツチン
グした後、オーバ・エツチング部でひさし状にな
つたフオトレジスト膜を熱的に軟化させ、オー
バ・エツチング部でフオトレジスト膜と被加工材
料とを密着させ、フオトレジスト膜をマスクにし
て被加工材料を加工し、その後、フオトレジスト
膜を除去し、所定の加工工程を経た後、オーバ・
エツチングによりパターニングされている第２の
加工マスク材料をマスクにして被加工材料を加工
する。(4) General description of the invention A second processing mask material is formed under a photoresist film using one type of photomask, and the second processing mask material is formed to a desired size using the patterned photoresist film as a mask. After over-etching, the photoresist film that has formed a canopy in the over-etched area is thermally softened, and the photoresist film and the workpiece are brought into close contact with each other in the over-etched area, using the photoresist film as a mask. After processing the material to be processed, removing the photoresist film and going through the prescribed processing steps,
The material to be processed is processed using the second processing mask material that has been patterned by etching as a mask.
とくに本発明の要点は、ひさし状になつたフオ
トレジスト膜を軟化させ、被加工材料に密着さ
せ、自己整合的に、被加工材料を少なくとも２回
以上加工するところにある。 In particular, the gist of the present invention is to soften the eaves-shaped photoresist film, bring it into close contact with the material to be processed, and process the material to be processed at least twice in a self-aligning manner.
(5) 実施例
以下、本発明を実施例を参照して詳細に説明す
る。なお、以下の説明は本発明のフオトレジスト
法を半導体装置の製造方法に適用しておこなう
が、本発明の精神を逸脱することなく種々の変形
が有り得ることに注意されねばならない。(5) Examples Hereinafter, the present invention will be explained in detail with reference to examples. In the following explanation, the photoresist method of the present invention will be applied to a method of manufacturing a semiconductor device, but it must be noted that various modifications may be made without departing from the spirit of the present invention.
２つの実施例について、説明する。 Two examples will be described.
第１図におけるａ乃至ｅは本発明の第１の実施
例を示し、オフセツト・ゲートのｎチヤンネル
MOSトランジスタの製造工程に本発明を適用し
た例である。 A to e in FIG. 1 indicate a first embodiment of the present invention, in which n-channels of offset gates are shown.
This is an example in which the present invention is applied to a manufacturing process of a MOS transistor.
ａはｐ型100面で、基板比抵抗が10Ωcmのシリ
コン基板１上に、1000℃，60分のドライ熱酸化に
よつて厚さ50nmのシリコン酸化膜２を形成し、
その上にCVD法によつて厚さ350nmの多結晶シ
リコン３を堆積し、リンの不純物ドーブをした後
に、厚さ100nmの薄い熱酸化膜４を750℃，60分
のウエツト熱酸化によつて形成し、その上にゲー
ト電極を形成するため、５μｍの幅のフオトレジ
スト膜５を形成したところまでを示す。なおフオ
トレジスト材はAzoplate Shiplay社のAz1350Jを
用いた。処理条件はこのフオトレジストの標準の
条件に従つた。 A is a p-type 100 plane, and a silicon oxide film 2 with a thickness of 50 nm is formed on a silicon substrate 1 with a substrate resistivity of 10 Ωcm by dry thermal oxidation at 1000° C. for 60 minutes.
Polycrystalline silicon 3 with a thickness of 350 nm is deposited thereon by the CVD method, and after doping with phosphorus impurity, a thin thermal oxide film 4 with a thickness of 100 nm is deposited by wet thermal oxidation at 750°C for 60 minutes. The photoresist film 5 having a width of 5 μm is shown in order to form a gate electrode thereon. The photoresist material used was Az1350J manufactured by Azoplate Shiplay. Processing conditions followed standard conditions for this photoresist.
ｂは、その後、フオトレジスト膜５をマスクと
して、熱酸化膜４を、６対１の弗化アンモニウ
ム／弗化水素酸エツチ液中で、10分間エツチング
したところまでを示す。このとき、エツチ液の熱
酸化膜のエツチング速度は、液温20℃のとき、
100nm／分であり、熱酸化膜４は、フオトレジス
ト膜端から１μｍのサイド・エツチングが進んで
いる。熱酸化膜４のエツチングの際、エツチ液の
液温を十分に設定値20℃に保つように管理すれ
ば、サイド・エツチングの寸法バラツキならびに
形状バラツキは十分に小さくおさえることができ
た。 Part b shows that the thermal oxide film 4 was then etched for 10 minutes in a 6:1 ammonium fluoride/hydrofluoric acid etchant using the photoresist film 5 as a mask. At this time, the etching rate of the thermal oxide film of the etchant is as follows:
The etching rate is 100 nm/min, and side etching of the thermal oxide film 4 is progressing by 1 μm from the edge of the photoresist film. When etching the thermal oxide film 4, if the temperature of the etchant was sufficiently maintained at the set value of 20°C, the dimensional and shape variations in side etching could be kept sufficiently small.
ｃは、その後、140℃，10分のベーキングをお
こない、フオトレジスト膜５を軟化させ、熱酸化
膜４のサイド・エツチングによつてできたフオト
レジスト膜５と多結晶シリコン３の間隙をなくす
るよう、フオトレジスト膜５を多結晶シリコン３
上に落下させたところまでを示す。 After that, baking is performed at 140°C for 10 minutes to soften the photoresist film 5 and eliminate the gap between the photoresist film 5 and the polycrystalline silicon 3 created by side etching of the thermal oxide film 4. In this way, the photoresist film 5 is replaced with polycrystalline silicon 3.
It shows the point where it is dropped.
ｄは、その後、フオトレジスト膜５をマスクに
して、多結晶シリコン３をプラズマ・エツチング
によつて加工し、フオトレジスト膜５を除去した
後、高濃度拡散層領域６−１および６−２を、打
込みエネルギ150keV、打込み量６×1015cm-2のヒ
素打込みによつて形成したところまでを示す。 d, the polycrystalline silicon 3 is then processed by plasma etching using the photoresist film 5 as a mask, and after removing the photoresist film 5, the high concentration diffusion layer regions 6-1 and 6-2 are etched. , the part formed by arsenic implantation with an implantation energy of 150 keV and an implantation amount of 6×10 15 cm -2 is shown.
ｅは、その後、熱酸化膜４をマスクにして、多
結晶シリコン３をプラズマ・エツチングによつて
再度加工した後、低濃度拡散領域７−１および７
−２を、打込みエネルギ100keV、打込み量２×
1012cm-2のヒ素打込みによつて形成したところま
でを示す。 After that, the polycrystalline silicon 3 is processed again by plasma etching using the thermal oxide film 4 as a mask, and then the low concentration diffusion regions 7-1 and 7 are etched.
-2, implant energy 100keV, implant amount 2×
The part formed by arsenic implantation of 10 12 cm -2 is shown.
その後は、通常の半導体プロセスにしたがつて
オフセツト・ゲームのｎチヤンネルMOSトラン
ジスタが作製される。本実施例は、本発明のフオ
トレジスト法をオフセツト・ゲート部の寸法を自
己整合的に決めるために用いたもので、第２の加
工マスク材料としては、多結晶シリコン３を熱酸
化することにより形成されるSiO2膜４を利用
し、被加工材料は、多結晶シリコン３である。こ
の結果、オフセツト・ゲートのｎチヤンネル
MOSトランジスタとしては、オフセツト長の寸
法バラツキならびに形状バラツキが非常に小さ
く、高耐圧化されたMOSトランジスタが実現で
き、しかも微細加工にも適し、高集積化可能なオ
フセツト・ゲートMOSトランジスタが実現でき
た。 Thereafter, an offset game n-channel MOS transistor is manufactured according to a normal semiconductor process. In this example, the photoresist method of the present invention was used to determine the dimensions of the offset gate portion in a self-aligned manner, and as the second processing mask material, polycrystalline silicon 3 was thermally oxidized. Using the formed SiO 2 film 4, the material to be processed is polycrystalline silicon 3. As a result, the n-channel of the offset gate
As a MOS transistor, we were able to realize a MOS transistor with very small dimensional variations in offset length and shape variation, and a high breakdown voltage.In addition, we were able to realize an offset gate MOS transistor that is suitable for microfabrication and can be highly integrated. .
第２図におけるａ乃至ｅは、本発明の第２の実
施例を示し、半導体メモリのメモリ・セルの製造
工程に本発明を適用した例である。 A to e in FIG. 2 show a second embodiment of the present invention, which is an example in which the present invention is applied to a manufacturing process of a memory cell of a semiconductor memory.
ａは、ｐ型100面で、基板比抵抗が10Ω・cmの
シリコン基板１１上に、アイソレーシヨン用選択
酸化膜１２−１および１２−２を形成した後、厚
さ50nmのシリコン酸化膜１３を形成し、その上
にCVD法によつて厚さ350nmの多結晶シリコン
１４を堆積し、高濃度にリンの不純物ドープをお
こなつた後、厚さ100nmの熱酸化膜１５を850
℃，30分のウエツト熱酸化によつて形成し、その
上に多結晶シリコン１４を加工するため、フオト
レジスト膜１６を塗布し、パターニングしたとこ
ろまでを示す。 After forming selective oxide films 12-1 and 12-2 for isolation on a p-type 100-plane silicon substrate 11 with a substrate resistivity of 10 Ω·cm, a silicon oxide film 13 with a thickness of 50 nm is formed. A polycrystalline silicon 14 with a thickness of 350 nm is deposited thereon by the CVD method, and after doping with a high concentration of phosphorus, a thermal oxide film 15 with a thickness of 100 nm is deposited on the polycrystalline silicon 14 with a thickness of 850 nm.
The photoresist film 16 is formed by wet thermal oxidation for 30 minutes at 30°C, and the photoresist film 16 is applied and patterned in order to process the polycrystalline silicon 14 thereon.
ｂは、その後、フオトレジスト膜１６をマスク
として、熱酸化膜１５を、6/1の弗化アンモニウ
ム／弗酸エツチ液中で、20分間エツチングしたと
ころまでを示す。このとき、熱酸化膜１５は、フ
オトレジスト膜下まで２μｍのサイドエツチング
が進んでいる。このサイド・エツチング幅が、メ
モリ・セルの転送トランジスタのチヤネル長に相
当する。 Part b shows that the thermal oxide film 15 was then etched for 20 minutes in a 6/1 ammonium fluoride/hydrofluoric acid etchant using the photoresist film 16 as a mask. At this time, side etching of the thermal oxide film 15 by 2 μm has progressed to below the photoresist film. This side etching width corresponds to the channel length of the transfer transistor of the memory cell.
ｃは、その後、140℃，10分のベーキングをお
こない、フオトレジスト膜１６を軟化させ、熱酸
化膜１５のサイド・エツチングによつてできたフ
オトレジスト膜１６と熱酸化膜１５の間隙をなく
するよう、フオトレジスト膜１６を多結晶シリコ
ン１４上に落下させ密着させたところまでを示
す。 c is then baked at 140° C. for 10 minutes to soften the photoresist film 16 and eliminate the gap between the photoresist film 16 and the thermal oxide film 15 created by side etching of the thermal oxide film 15. The photoresist film 16 is shown dropped onto the polycrystalline silicon 14 and brought into close contact with the polycrystalline silicon 14.
ｄは、その後、フオトレジスト膜１６をマスク
にして、多結晶シリコン１４をプラズマ・エツチ
ングによつて加工し、フオトレジスト膜１６を除
去した後、メモリ・セルのデータ線を形成するた
め高濃度拡散層領域１７を、打込みエネルギ
150keV、打込み量１×1016cm-2のヒ素打込みによ
つて形成したところまでを示す。 Then, using the photoresist film 16 as a mask, the polycrystalline silicon 14 is processed by plasma etching, and after removing the photoresist film 16, high concentration diffusion is performed to form the data line of the memory cell. The layer region 17 is exposed to the implant energy.
The area formed by arsenic implantation at 150 keV and an implantation amount of 1×10 16 cm −2 is shown.
ｅは、その後、熱酸化膜１５をマスクにして多
結晶シリコン１４をプラズマ・エツチングによつ
て再度加工した後、熱酸化膜１５と基板表面上の
50nmの酸化膜１３を除去した後、750℃，90分の
ウエツト酸化と、ひき続いて1000℃，45分のドラ
イ酸化とをおこない、転送トランジスタ部に厚さ
50nmの熱酸化膜１８と、多結晶シリコン１４の
周囲と拡散層領域１７の上に、それぞれ厚さ
250nmの熱酸化膜２０と１９を形成する。さらに
転送トランジスタの電極と半導体メモリのワード
線とを兼ねる電極配線２１を形成したところまで
を示す。 After that, the polycrystalline silicon 14 is processed again by plasma etching using the thermal oxide film 15 as a mask, and then the thermal oxide film 15 and the substrate surface are etched.
After removing the 50nm oxide film 13, wet oxidation at 750°C for 90 minutes, followed by dry oxidation at 1000°C for 45 minutes, was performed to reduce the thickness of the transfer transistor area.
A thermal oxide film 18 with a thickness of 50 nm, a thickness around the polycrystalline silicon 14 and on the diffusion layer region 17, respectively
250 nm thermal oxide films 20 and 19 are formed. Furthermore, the state where an electrode wiring 21 serving both as an electrode of a transfer transistor and a word line of a semiconductor memory is formed is shown.
その後は、通常の半導体プロセスにしたがつて
半導体メモリが作製される。本実施例は、本発明
のフオトレジスト法をメモリ・セルの転送トラン
ジスタのチヤンネル長を自己整合的に決めるため
に用いたものである。第２の加工マスク材料とし
ては多結晶シリコン１４を熱酸化することにより
形成されるSiO2膜１５を利用し、被加工材料は
多結晶シリコン１４である。この結果、転送トラ
ンジスタのチヤンネル長バラツキが小さくなつた
他に、不純物濃度依存性を利用した選択酸化技術
とを組み合わせることにより、メモリ・セル・ア
レー内には、転送電極とワード線配線とのコンタ
クトを必要とない、高集積半導体メモリの実現が
可能となつた。 After that, a semiconductor memory is manufactured according to a normal semiconductor process. In this embodiment, the photoresist method of the present invention is used to determine the channel length of a transfer transistor of a memory cell in a self-aligned manner. As the second processing mask material, an SiO 2 film 15 formed by thermally oxidizing polycrystalline silicon 14 is used, and the material to be processed is polycrystalline silicon 14. As a result, in addition to reducing channel length variations in transfer transistors, by combining selective oxidation technology that utilizes impurity concentration dependence, contacts between transfer electrodes and word line interconnects are formed in memory cell arrays. It has become possible to realize highly integrated semiconductor memory that does not require
(6) まとめ
以上説明してきた本発明のフオトレジスト加工
法によれば、一種類のマスクを用いて、自己整合
的に少なくとも２回以上の加工が可能となり、し
かも加工の制御性、さらに加工形状が十分に満足
でき、微細加工法に新しい技術を提供したと云え
る。本発明の要点は、フオトレジスト膜を軟化さ
せることにより、落下さらに密着させるところに
集約し、その方法の応用として高性能な自己整合
オフセツト・ゲートMOSトランジスタの実現、
半導体メモリの高集積化の実現等を可能にした。
しかしながら、本発明の精神によれば、落下、密
着し得る材料であれば、その物質はフオトレジス
ト材料に限ることなく適用でき、また実施例とし
て半導体装置を上げてきたが、必ずしも半導体装
置だけに限定されるものでもなく広く応用が可能
である。なお、以上において、フオトレジストと
してAZ1350Jを用いて説明したが、ここでフオト
レジストというのは、単に光硬化性樹脂をさすだ
けでなく、電子線硬化性樹脂なども含み、放射線
硬化性樹脂を広くさすものとして用いている。要
するに、加熱によりある程度の軟化性が生じ、自
重により変形可能で、さらに加工材料とある程度
密着すればよい。(6) Summary According to the photoresist processing method of the present invention as explained above, it is possible to perform processing at least twice or more in a self-aligned manner using one type of mask, and it is possible to improve processing controllability and processing shape. was fully satisfied, and it can be said that we have provided a new technology for microfabrication. The main point of the present invention is to soften the photoresist film so that it falls further into contact with the photoresist film, and as an application of this method, realizes a high-performance self-aligned offset gate MOS transistor.
This made it possible to achieve higher integration levels in semiconductor memory.
However, according to the spirit of the present invention, the material is not limited to the photoresist material, as long as it is a material that can be dropped and adhered, and although a semiconductor device has been cited as an example, it is not necessarily applicable only to a semiconductor device. It is not limited and can be widely applied. Although the above explanation uses AZ1350J as a photoresist, photoresist here refers not only to photocurable resins, but also includes electron beam curable resins, and broadly refers to radiation curable resins. It is used as something to be admired. In short, it is sufficient that the material has a certain degree of softening property due to heating, can be deformed by its own weight, and has a certain degree of close contact with the processing material.
第１図のａ乃至ｅ、第２図のａ乃至ｅは、本発
明のフオトレジスト法を、それぞれオフセツト・
ゲートMOSトランジスタ、半導体メモリに適用
したときの、その製造工程を示した断面図。
Figures a to e in Figure 1 and a to e in Figure 2 illustrate the photoresist method of the present invention, respectively, with offset
A cross-sectional view showing the manufacturing process when applied to a gate MOS transistor and a semiconductor memory.
Claims (1)
エツチング液に対する耐性の異なる材料からなる
マスク材料膜および所望の形状ち有するレジスト
膜を順次積層して形成する工程と、上記レジスト
膜をマスクにして上記マスク材料膜の露出部分を
エツチして除きさらにサイドエツチする工程と、
上記被加工材料膜のうち、上記レジスト膜の下に
ある部分を残し、上記レジスト膜の外側にある部
分を除去して、上記レジスト膜の外側の部分の上
記基体の表面を露出する工程と、上記レジスト膜
を除去する工程と、上記マスク材料膜をマスクに
用いて上記被加工材料膜の露出された部分を除去
し、上記基体の表面を露出する工程を少なくとも
含む材料加工法。1. A step of sequentially laminating and forming on a substrate a material film to be processed, a mask material film made of a material having different resistance to an etching solution from the material film to be processed, and a resist film having a desired shape; Etching and removing the exposed portion of the mask material film using a mask, and further etching the side;
leaving a portion of the material film to be processed under the resist film and removing a portion outside the resist film to expose the surface of the substrate outside the resist film; A material processing method including at least the steps of removing the resist film, and using the mask material film as a mask to remove the exposed portion of the material film to be processed to expose the surface of the base.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP12093777A JPS5454577A (en) | 1977-10-11 | 1977-10-11 | Material working method with photo resist |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP12093777A JPS5454577A (en) | 1977-10-11 | 1977-10-11 | Material working method with photo resist |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS5454577A JPS5454577A (en) | 1979-04-28 |
| JPS6238852B2 true JPS6238852B2 (en) | 1987-08-20 |
Family
ID=14798649
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP12093777A Granted JPS5454577A (en) | 1977-10-11 | 1977-10-11 | Material working method with photo resist |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS5454577A (en) |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US4818715A (en) * | 1987-07-09 | 1989-04-04 | Industrial Technology Research Institute | Method of fabricating a LDDFET with self-aligned silicide |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS50134579A (en) * | 1974-04-13 | 1975-10-24 | ||
| JPS5235980A (en) * | 1975-09-16 | 1977-03-18 | Hitachi Ltd | Manufacturing method of semiconductor device |
-
1977
- 1977-10-11 JP JP12093777A patent/JPS5454577A/en active Granted
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS50134579A (en) * | 1974-04-13 | 1975-10-24 | ||
| JPS5235980A (en) * | 1975-09-16 | 1977-03-18 | Hitachi Ltd | Manufacturing method of semiconductor device |
Also Published As
| Publication number | Publication date |
|---|---|
| JPS5454577A (en) | 1979-04-28 |
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