JPS5720451A - Semiconductor device - Google Patents

Semiconductor device

Info

Publication number
JPS5720451A
JPS5720451A JP9518880A JP9518880A JPS5720451A JP S5720451 A JPS5720451 A JP S5720451A JP 9518880 A JP9518880 A JP 9518880A JP 9518880 A JP9518880 A JP 9518880A JP S5720451 A JPS5720451 A JP S5720451A
Authority
JP
Japan
Prior art keywords
layer
allowance
poly
semiconductor device
slippage
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP9518880A
Other languages
Japanese (ja)
Other versions
JPS6217870B2 (en
Inventor
Akira Ando
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Mitsubishi Electric Corp
Original Assignee
Mitsubishi Electric Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Mitsubishi Electric Corp filed Critical Mitsubishi Electric Corp
Priority to JP9518880A priority Critical patent/JPS5720451A/en
Publication of JPS5720451A publication Critical patent/JPS5720451A/en
Publication of JPS6217870B2 publication Critical patent/JPS6217870B2/ja
Granted legal-status Critical Current

Links

Landscapes

  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Weting (AREA)

Abstract

PURPOSE:To prevent disconnection by a method wherein the second poly Si layer is stacked on th first poly Si layer in a shape that crosses at right angles, an allowance for a slippage of mask matching is given and the second layer is bent. CONSTITUTION:The first layer and the second layer in poly Si are approximately crossed at right angles, the allowance for the slippage of mask matching is given and the second layer 4 is bent. According to this constitution, the second layer 4 is not disconnected at the edge of the first layer. The setting of 1mu or more is effecteve as the allowance l.
JP9518880A 1980-07-11 1980-07-11 Semiconductor device Granted JPS5720451A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP9518880A JPS5720451A (en) 1980-07-11 1980-07-11 Semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP9518880A JPS5720451A (en) 1980-07-11 1980-07-11 Semiconductor device

Publications (2)

Publication Number Publication Date
JPS5720451A true JPS5720451A (en) 1982-02-02
JPS6217870B2 JPS6217870B2 (en) 1987-04-20

Family

ID=14130772

Family Applications (1)

Application Number Title Priority Date Filing Date
JP9518880A Granted JPS5720451A (en) 1980-07-11 1980-07-11 Semiconductor device

Country Status (1)

Country Link
JP (1) JPS5720451A (en)

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH02118753U (en) * 1989-03-09 1990-09-25
JPH0416183U (en) * 1990-05-31 1992-02-10

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS4889684A (en) * 1972-02-24 1973-11-22
JPS515959A (en) * 1974-07-03 1976-01-19 Suwa Seikosha Kk Handotaisochino seizohoho

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS4889684A (en) * 1972-02-24 1973-11-22
JPS515959A (en) * 1974-07-03 1976-01-19 Suwa Seikosha Kk Handotaisochino seizohoho

Also Published As

Publication number Publication date
JPS6217870B2 (en) 1987-04-20

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