JPS5518022A - Method of forming wiring or electrode - Google Patents

Method of forming wiring or electrode

Info

Publication number
JPS5518022A
JPS5518022A JP9049478A JP9049478A JPS5518022A JP S5518022 A JPS5518022 A JP S5518022A JP 9049478 A JP9049478 A JP 9049478A JP 9049478 A JP9049478 A JP 9049478A JP S5518022 A JPS5518022 A JP S5518022A
Authority
JP
Japan
Prior art keywords
sio
groove
substrate
polysilicon
width
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP9049478A
Other languages
Japanese (ja)
Inventor
Seiichi Iwamatsu
Mitsuru Ogawa
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
CHIYOU LSI GIJUTSU KENKYU KUMIAI
CHO LSI GIJUTSU KENKYU KUMIAI
Original Assignee
CHIYOU LSI GIJUTSU KENKYU KUMIAI
CHO LSI GIJUTSU KENKYU KUMIAI
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by CHIYOU LSI GIJUTSU KENKYU KUMIAI, CHO LSI GIJUTSU KENKYU KUMIAI filed Critical CHIYOU LSI GIJUTSU KENKYU KUMIAI
Priority to JP9049478A priority Critical patent/JPS5518022A/en
Publication of JPS5518022A publication Critical patent/JPS5518022A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
    • H01L29/42312—Gate electrodes for field effect devices
    • H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
    • H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
    • H01L29/42356—Disposition, e.g. buried gate electrode
    • H01L29/4236—Disposition, e.g. buried gate electrode within a trench, e.g. trench gate electrode, groove gate electrode
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66568—Lateral single gate silicon transistors
    • H01L29/66613—Lateral single gate silicon transistors with a gate recessing step, e.g. using local oxidation
    • H01L29/66621—Lateral single gate silicon transistors with a gate recessing step, e.g. using local oxidation using etching to form a recess at the gate location

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Ceramic Engineering (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Manufacturing & Machinery (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Abstract

PURPOSE: To provide a wiring or an electrode of an extremely small width in a groove at the substantially per-pendicular side surface on the main surface of a simiconductor substrate thereby to miniaturize the device.
CONSTITUTION: When an N-type Si substrate 1 in a facial direction (110) is subjected to an anisotropic etching by use of a resist mask having a width of 0.3 μm, vertical etching mainly proceeds based on the difference between the etching speed of a face (110) and that of a face (100), and a groove having a width of 0.3 μm and a depth of 0.3 μ can be formed and the side surface of a groove 1a and the bottom surface assume facial directions as shown by (111) and (110). Then, the substrate 1 is coated with SiO23, and a p-type polysilicon layer 4 is laminated thereon. Then, the polysilicon layer 4 is subjected to a high temperature treatment in dry O2, and polysilicon 4a in the groove 1a is removed and polysilicon on SiO23 on the main surface of the N type silicon substrate 1 is converted to SiO25. The membrane 5 is etched by a mask 6 to provide an indentation 5a and the thickness of SiO2 at this portion is made into 0.3 μm. B ions are injected to produce P+ layers 7 and 8, and openings are made selectively on the membranes 5 and 3 and electrodes 9 and 10 are attached thereto. By this method a fine wiring or electrode forming device can be fabricated.
COPYRIGHT: (C)1980,JPO&Japio
JP9049478A 1978-07-26 1978-07-26 Method of forming wiring or electrode Pending JPS5518022A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP9049478A JPS5518022A (en) 1978-07-26 1978-07-26 Method of forming wiring or electrode

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP9049478A JPS5518022A (en) 1978-07-26 1978-07-26 Method of forming wiring or electrode

Publications (1)

Publication Number Publication Date
JPS5518022A true JPS5518022A (en) 1980-02-07

Family

ID=14000059

Family Applications (1)

Application Number Title Priority Date Filing Date
JP9049478A Pending JPS5518022A (en) 1978-07-26 1978-07-26 Method of forming wiring or electrode

Country Status (1)

Country Link
JP (1) JPS5518022A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6495883B2 (en) 2001-02-06 2002-12-17 Denso Corporation Trench gate type semiconductor device and method of manufacturing

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6495883B2 (en) 2001-02-06 2002-12-17 Denso Corporation Trench gate type semiconductor device and method of manufacturing

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