JPH10508154A - シリコンセグメントのための垂直相互接続方法 - Google Patents
シリコンセグメントのための垂直相互接続方法Info
- Publication number
- JPH10508154A JPH10508154A JP8503164A JP50316496A JPH10508154A JP H10508154 A JPH10508154 A JP H10508154A JP 8503164 A JP8503164 A JP 8503164A JP 50316496 A JP50316496 A JP 50316496A JP H10508154 A JPH10508154 A JP H10508154A
- Authority
- JP
- Japan
- Prior art keywords
- segments
- stack
- segment
- electrically conductive
- wafer
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
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Classifications
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- H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L24/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
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- H01L23/36—Selection of materials, or shaping, to facilitate cooling or heating, e.g. heatsinks
- H01L23/373—Cooling facilitated by selection of materials for the device or materials for thermal expansion adaptation, e.g. carbon
- H01L23/3737—Organic materials with or without a thermoconductive filler
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- H01L23/4824—Pads with extended contours, e.g. grid structure, branch structure, finger structure
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- H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
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- H01L23/5256—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body with adaptable interconnections comprising fuses, i.e. connections having their state changed from conductive to non-conductive
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- H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
- H01L23/5382—Adaptable interconnections, e.g. for engineering changes
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- H01L25/065—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00
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- H01R29/00—Coupling parts for selective co-operation with a counterpart in different ways to establish different circuits, e.g. for voltage selection, for series-parallel selection, programmable connectors
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- H01R4/00—Electrically-conductive connections between two or more conductive members in direct contact, i.e. touching one another; Means for effecting or maintaining such contact; Electrically-conductive connections having two or more spaced connecting locations for conductors and using contact members penetrating insulation
- H01R4/04—Electrically-conductive connections between two or more conductive members in direct contact, i.e. touching one another; Means for effecting or maintaining such contact; Electrically-conductive connections having two or more spaced connecting locations for conductors and using contact members penetrating insulation using electrically conductive adhesives
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- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/30—Assembling printed circuits with electric components, e.g. with resistor
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- H05K3/305—Affixing by adhesive
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- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/30—Assembling printed circuits with electric components, e.g. with resistor
- H05K3/32—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits
- H05K3/321—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by conductive adhesives
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- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K7/00—Constructional details common to different types of electric apparatus
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Abstract
Description
Claims (1)
- 【特許請求の範囲】 1.前記セグメント上の複数のダイで、各々のダイは複数の第1の接続パッド を含むものと、 外部電気接続のために前記セグメントの前記縁の1より多くに位置してい る複数の縁接続パッドと、 前記ダイを相互接続するための前記複数の第1接続パッド間に接続された 金属跡の層で、前記ダイを前記外部接続に接続するため、前記金属層は、前記複 数の縁接続パッドと前記複数の第1接続パッドとの間をさらに接続しているもの とを有するセグメントを画定する3つ以上の縁を持つシリコンの前記セグメント 。 2.前記金属跡がクロムとチタニウム・タングステンと金のサンドイッチを含 む請求項1のシリコンのセグメント。 3.前記セグメントがさらに前面と裏面を含み、前記複数の第1接続パッドと 前記複数の縁接続パッドと前記金属跡の層が前記セグメントの前記前面に位置し ている請求項2のシリコンのセグメント。 4.前記セグメントを画定する前記縁がさらに縁壁を含み、該縁壁と前記セグ メントの裏面が窒化ケイ素で絶縁されている請求項3のシリコンのセグメント。 5.前記縁壁が斜角を付けられた請求項4のシリコンのセグメント。 6.互いの上部に配置されるセグメントの積層であり、前記セグメントの各々 が3つ以上の縁と、その中に電気回路機構を有する複数のダイと、電気的に伝導 性の接触点とを含むものと、 前記セグメントの各々の前記複数のダイを相互接続するため、及び前記複 数のダイの1以上を前記セグメントの各々の前記電気的に伝導性の接触点の1以 上へ接続するための第1の相互接続手段と、 前記セグメントの各々の前記電気的に伝導性の接触点へアクセスを提供す るアクセス手段と、 前記積層内の前記セグメントの各々の前記電気的に伝導性の接触点を電気 的に相互接続するため、及び前記積層内の前記セグメントの各々に位置している 前記複数のダイへ側面の電気的接続を提供するための、前記アクセス手段に適応 できる第2の相互接続手段とを有する電気回路機構の積層。 7.前記電気的に伝導性の接触点が前記セグメントの各々の前記縁の1より多 くに沿って位置している請求項6の電気回路機構の積層。 8.前記第1の相互接続手段が金属跡の1層より多くを含む請求項7の電気回 路機構の積層。 9.前記金属跡の層がクロム、チタニウム・タングステン、金のサンドイッチ を含む請求項8の電気回路機構の積層。 10.前記アクセス手段が前記セグメントの前記縁の各々に沿って内方に傾斜し た縁壁を含んでいる請求項9の電気回路機構の積層。 11.前記相互接続手段が電気的に伝導性のエポキシを含む請求項10の電気回 路機構の積層。 12.前記セグメントの各々がコントロール接続パッドを含んでおり、前記セグ メントの各々の前記コントロール接続パッドに焼き付けられた独自のパターンを 有することにより前記セグメントがお互いに関して独自に作られた請求項11の 電気回路機構の積層。 13.前記セグメントが相互接続された機能ダイと非機能ダイとを含み、前記非 機能ダイは前記機能ダイから切り離され、前記機能ダイの特定の1つが前記非機 能ダイと置き替わるために前記セグメントの各々の前記金属跡が定められる請求 項11の電気回路機構の積層。 14.前記積層は6つの前記セグメントを含み、前記6つのセグメントの各々は 前記ダイの4つを含んでおり、前記積層は前記ダイの4つの垂直列を有し、前記 垂直列の各々は前記ダイの6つ分の高さであり、又、前記機能ダイの4つが前記 積層内の前記ダイの前記4つの垂直列で接続されるように前記電気的に伝導性の エポキシが前記6つのセグメントに適用される請求項12の電気回路機構の積層 。 15.複数のダイを有するウェハーを用意し、 複数のセグメントの各々の1つが前記ウェハーの前記ダイの複数の隣接す るグループによって形成されている前記複数のセグメントを製造し、 前記複数のセグメントの前記各々の1つの前記複数の隣接するダイを相互 接続し、 前記ウェハーから前記複数のセグメントの前記各々の1つを切り離し、 セグメントの積層であって前記積層が外部垂直面を有するものを製造する ために、前記複数のセグメントを互いの上部に置き、 前記セグメントの積層を電気的に相互接続する工程を有するセグメントの 積層形成方法。 16.さらに、前記複数のダイの各々に電気的に伝導性の内部接触点を用意し、 前記複数のセグメントの前記各々の1つに電気的に伝導性の外部接触点を 用意し、 前記複数のセグメントの前記各々の1つに、前記複数のダイ上の前記電気 的に伝導性の内部接触点と前記複数のセグメントの前記各々の1つ上の前記電気 的に伝導性の内部接触点との間に伸びる金属跡の層を用意し、 電気的に伝導性のエポキシが前記積層内の前記セグメントの前記各々の1 つの上の前記電気的に伝導性の外部接触点と接触するように、前記積層の前記外 部垂直面の1より多くに前記電気的に伝導性のエポキシを適用しそれによって前 記積層内の前記複数のセグメントを電気的に相互接続する工程を含む請求項15 のセグメントの積層形成方法。 17.さらに、前記セグメントの各々にコントロール接続パッドを用意し、 前記積層内の前記セグメントへのアクセスのために外部ソースから前記積 層へコントロールシグナルを供給し、 前記セグメントの各々の前記コントロール接続パッド内に独自のパターン を焼き付けることによって前記コントロールシグナルを前記セグメントの各々に とって独自に形成する工程を含む請求項16のセグメントの積層形成方法。 18.前記積層が頂上のセグメントを含んでおり、 さらに、その中に電気回路機構とホールを有するシグナル伝達基板を用意 し、 前記ホール内にセグメントの前記積層を取り付け、 前記シグナル伝達基板と前記積層の前記頂上のセグメントの前記電気的に 伝導性の外部接触点との間に電気的に伝導性のエポキシを適用することにより、 前記セグメントの積層を前記シグナル伝達基板と電気的に接続する工程を有する 請求項17のセグメントの積層形成方法。 19.前記頂上の積層が前記シグナル伝達基板の表面と共平面である請求項18 のセグメントの積層形成方法。 20.前記電気的に伝導性のエポキシ跡が実質上前記シグナル伝達基板と同じ平 面にある請求項19のセグメントの積層形成方法。 21.電気回路機構を有するシグナル伝達基板を用意し、 前記シグナル伝達基板内にホールをあけ、 前記積層の頂上が前記シグナル伝達基板の表面と共平面になるように、前 記ホール内に前記セグメントの積層を取り付け、 前記セグメントの積層を前記シグナル伝達基板に電気的に接続する工程を 有する、電気的に伝導性の接触点を有するシリコンセグメントの積層の取付方法 。 22.前記セグメントの積層を前記シグナル伝達基板に電気的に接続するために 、前記シグナル伝達基板と前記積層の前記電気的に伝導性の接触点との間に電気 的に伝導性のエポキシ跡を適用する工程を含む請求項21のシリコンセグメント の積層の取付方法。 23.前記跡が前記シグナル伝達基板と実質上同じ平面にあるように前記跡を設 ける工程を含む請求項22のシリコンセグメントの積層の取付方法。 24.前記セグメントの積層をプリント回路板に取り付け、PCカード内の前記 プリント回路板と前記セグメントの積層を封入する工程を含む請求項23のシリ コンセグメントの積層の取付方法。
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US08/265,081 | 1994-06-23 | ||
US08/265,081 US5675180A (en) | 1994-06-23 | 1994-06-23 | Vertical interconnect process for silicon segments |
PCT/US1995/006884 WO1996000494A1 (en) | 1994-06-23 | 1995-06-08 | Vertical interconnect process for silicon segments |
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JP2006220350A Division JP2007019527A (ja) | 1994-06-23 | 2006-08-11 | シリコンセグメントのための垂直相互接続方法 |
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JP2006220350A Pending JP2007019527A (ja) | 1994-06-23 | 2006-08-11 | シリコンセグメントのための垂直相互接続方法 |
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EP (2) | EP1158570B1 (ja) |
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KR (1) | KR100377657B1 (ja) |
AT (2) | ATE211350T1 (ja) |
AU (1) | AU2815395A (ja) |
DE (2) | DE69534976T2 (ja) |
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-
1995
- 1995-06-07 US US08/476,623 patent/US5661087A/en not_active Expired - Lifetime
- 1995-06-08 AT AT95923676T patent/ATE211350T1/de not_active IP Right Cessation
- 1995-06-08 EP EP01115235A patent/EP1158570B1/en not_active Expired - Lifetime
- 1995-06-08 WO PCT/US1995/006884 patent/WO1996000494A1/en active IP Right Grant
- 1995-06-08 AT AT01115235T patent/ATE325426T1/de not_active IP Right Cessation
- 1995-06-08 KR KR1019960707364A patent/KR100377657B1/ko not_active IP Right Cessation
- 1995-06-08 DE DE69534976T patent/DE69534976T2/de not_active Expired - Fee Related
- 1995-06-08 EP EP95923676A patent/EP0766909B1/en not_active Expired - Lifetime
- 1995-06-08 DE DE69524756T patent/DE69524756T2/de not_active Expired - Fee Related
- 1995-06-08 JP JP50316496A patent/JP3895768B2/ja not_active Expired - Fee Related
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-
1997
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-
2006
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US5675180A (en) | 1997-10-07 |
DE69524756D1 (de) | 2002-01-31 |
ATE325426T1 (de) | 2006-06-15 |
JP2007019527A (ja) | 2007-01-25 |
US5661087A (en) | 1997-08-26 |
KR100377657B1 (ko) | 2004-02-05 |
EP0766909B1 (en) | 2001-12-19 |
JP3895768B2 (ja) | 2007-03-22 |
WO1996000494A1 (en) | 1996-01-04 |
EP1158570A1 (en) | 2001-11-28 |
US6188126B1 (en) | 2001-02-13 |
DE69534976D1 (de) | 2006-06-08 |
TW271487B (ja) | 1996-03-01 |
DE69524756T2 (de) | 2002-08-14 |
AU2815395A (en) | 1996-01-19 |
DE69534976T2 (de) | 2006-12-28 |
ATE211350T1 (de) | 2002-01-15 |
EP0766909A1 (en) | 1997-04-09 |
US5837566A (en) | 1998-11-17 |
EP0766909A4 (en) | 1997-10-22 |
EP1158570B1 (en) | 2006-05-03 |
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