WO1994001887A1 - High density memory and method of forming the same - Google Patents

High density memory and method of forming the same Download PDF

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Publication number
WO1994001887A1
WO1994001887A1 PCT/US1993/006315 US9306315W WO9401887A1 WO 1994001887 A1 WO1994001887 A1 WO 1994001887A1 US 9306315 W US9306315 W US 9306315W WO 9401887 A1 WO9401887 A1 WO 9401887A1
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WIPO (PCT)
Prior art keywords
leads
memory
memory circuit
lead frame
lead
Prior art date
Application number
PCT/US1993/006315
Other languages
French (fr)
Inventor
Emory C. Garth
Clive Lankford, Iii
Original Assignee
Rtb Technology, Inc.
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Rtb Technology, Inc. filed Critical Rtb Technology, Inc.
Priority to AU46632/93A priority Critical patent/AU4663293A/en
Publication of WO1994001887A1 publication Critical patent/WO1994001887A1/en

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    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C5/00—Details of stores covered by group G11C11/00
    • G11C5/06—Arrangements for interconnecting storage elements electrically, e.g. by wiring
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C5/00—Details of stores covered by group G11C11/00
    • G11C5/02—Disposition of storage elements, e.g. in the form of a matrix array
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/495—Lead-frames or other flat leads
    • H01L23/49503—Lead-frames or other flat leads characterised by the die pad
    • H01L23/4951—Chip-on-leads or leads-on-chip techniques, i.e. inner lead fingers being used as die pad
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
    • H01L25/10—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices having separate containers
    • H01L25/105—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices having separate containers the devices being of a type provided for in group H01L27/00
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/10—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers
    • H01L2225/1005—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/1011—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00 the containers being in a stacked arrangement
    • H01L2225/1017—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00 the containers being in a stacked arrangement the lowermost container comprising a device support
    • H01L2225/1029—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00 the containers being in a stacked arrangement the lowermost container comprising a device support the support being a lead frame
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/10—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers
    • H01L2225/1005—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/1011—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00 the containers being in a stacked arrangement
    • H01L2225/1047—Details of electrical connections between containers
    • H01L2225/1058—Bump or bump-like electrical connections, e.g. balls, pillars, posts
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42—Wire connectors; Manufacturing methods related thereto
    • H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L24/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01014—Silicon [Si]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01057—Lanthanum [La]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/14—Integrated circuits
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
    • H01L2924/1901—Structure
    • H01L2924/1904—Component type
    • H01L2924/19041—Component type being a capacitor
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30—Technical effects
    • H01L2924/301—Electrical effects
    • H01L2924/3011—Impedance

Definitions

  • This invention relates in general to integrated circuits, and more particularly to a high density memory module.
  • DRAM dynamic random access memory
  • SRAM static random access memory
  • DIPs dual-inline packages
  • ZIPs Zero-Zag Inline Packages
  • SOJs Small Outline J-leaded
  • SIPs Single-inline packages
  • SIMMs single-inline memory module
  • a more modern solution is to interconnect a stack of memory circuits which are not contained in their typical package thereby effecting a greater density.
  • An example of this approach is "3-D Memory Multichip Modules" from Texas Instruments.
  • Present implementations of this approach present significant problems.
  • the stacked memory circuits suffer from thermal problems, particularly affecting those memory circuits in the middle of the stack where the heat is not adequately dissipated.
  • the complexity of manufacturing the stacked memory circuits results in a relatively high cost in comparison with other packaging options.
  • Third, testing of the memory circuits is difficult.
  • a high density memory module and method of forming the same is provided.
  • the memory module has safe thermal characteristics, high testability, and may be fabricated using uncomplicated procedures.
  • the memory module comprises a plurality of memory subassemblies, wherein each subassembly includes a memory circuit, a lead frame having a plurality of leads coupled to the memory circuit, and encapsulating material surrounding the memory circuit and the lead frame, such that the leads extend outwardly from the encapsulating material to allow convective heat transfer.
  • Connectors couple the respective leads of the memory subassemblies outside the encapsulating material to electrically couple the memory circuits.
  • the leads extend outwardly from the encapsulating material such that each of the memory circuits may dissipate heat by conductive heat transfer through the leads to a convective surface.
  • the convective surface area can be adjusted for optimum heat transfer by adjusting the length of the lead outside the encapsulating material.
  • packaging of the memory circuit by the encapsulating material may be performed such that the leads may be used for testing prior to final assembly.
  • each lead frame has an identical layout such that predefined portions of the lead frame may be removed to provide a unique circuit configuration corresponding to the position of the memory circuit in the stack. The use of a single lead frame layout greatly simplifies the construction of the memory module.
  • FIGURE la illustrates a perspective view of the high density memory module (HDMM);
  • FIGURE lb illustrates a pin-out for the HDMM of FIGURE la;
  • FIGURE 2 illustrates a schematic representation of the high density memory module ;
  • FIGURE 3a illustrates a top view of a 1 M x 1 DRAM circuit showing the interconnection pads;
  • FIGURE 3b illustrates a top view of a lead frame;
  • FIGURE 4a illustrates a top view of the encapsulated RAM prior to assembly, showing the lead frame test points;
  • FIGURE 4b illustrates an encapsulated DRAM subassembly prior to final assembly with cutaway views of the memory circuit and lead frame;
  • FIGURE 5 illustrates a bottom perspective view of the bottom header of the memory module;
  • FIGURE 6 illustrates an exploded view of the memory module;
  • FIGURE 7a illustrates a top view of a 1 M x 4 DRAM circuit showing the interconnection pads; and
  • FIGURE 7b illustrates
  • FIGURE 1 illustrates a perspective view of a high density memory module (HDMM).
  • the HDMM 10 comprises a plurality of stacked subassemblies 12 having protruding leads 14. Pins 16 are positioned through respective aligned leads 14. The pins 16 terminate in ends 18 which may be attached directly to a circuit board or inserted into a socket which is attached to a circuit board.
  • a bottom header 19a and top header 19b are positioned at the bottom and top, respectively, of the HDMM 10.
  • Each subassembly 12 includes a memory circuit coupled to a lead frame which has been encapsulated in a dielectric packaging material 13, with the leads 14 protruding from the packaging material.
  • the lead frames are described in greater detail in connection with FIGURE 3b.
  • Pins 16 provide electrical connections in the third (vertical) dimension to distribute the appropriate signals to multiple memory circuits.
  • the subassemblies 12 may be configured in groups of eight (or nine to include a parity bit) to form bytes of digital data. The number of stacked subassemblies may be increased or decreased in order to provide a desired word size or an alternative configuration.
  • the HDMM will be described in connection with a 1 Mbit x 9 dynamic random access memory module, although other configurations can be easily designed.
  • the lead frames In addition to distributing signals from the memory circuits, the lead frames also provide thermal management. Heat from the memory circuits is conducted to the exterior of the HDMM by leads 14, which are cooled by the ambient air.
  • leads 14 Using a memory circuit having dimensions of approximately 0.180 x 0.400 inches (.4572 x 1.016 cm), an HDMM 10 may be formed having dimensions of approximately 0.340 x 0.475 x 0.435 inches (.8636 x 1.2065 x 1.1049 cm) using a stack of nine subassemblies 12.
  • the HDMM achieves a packaging density approaching the practical maximum possible as limited by the physical size of the silicon, the lead frame and the necessary encapsulation for environmental protection.
  • FIGURE lb illustrates a pin-out of the HDMM 10.
  • a 1 Mbit x 9 DRAM module ten address pins (A ⁇ -Ag), nine data inputs (D j -Dg), and nine data outputs (Qj-Qg) are provided.
  • CAS, RAS and W provide the control signals to read and write to the HDMM.
  • N ss and N cc provide the power to the HDMM.
  • FIGURE 2 illustrates a schematic representation of the interconnections between the memory circuits and the pins of the HDMM 10.
  • the pin numbers referenced to the pin-out of FIGURE lb, are shown parenthetically.
  • Address pins A Q -Agare coupled to respective inputs for each of the memory circuits 20a- 20i.
  • N cc , N ss , RAS, CAS and W pins are coupled to respective inputs of the memory circuits 20a-20i.
  • the data inputs D j -Dg and data outputs Q ⁇ -Qg are coupled to the data inputs (D) and data outputs (Q) of respective memory chips 20a-20i.
  • D ⁇ is coupled to data input D of memory circuit 20a
  • D 2 is coupled to data input D of memory circuit 20b
  • D 3 is coupled to data input D of memory circuit 20c
  • j ⁇ is coupled to data output Q of memory circuit 20a
  • 2 is coupled to data output Q of memory circuit 20b
  • Q 3 is coupled to data output Q of memory circuit 20c.
  • nine bits of data may be either written to, or read from, the HDMM 10.
  • Decoupling capacitors 22 a- d are coupled between N cc and N ss .
  • FIGURE 3a illustrates a top view of an exemplary memory circuit 20. Signals from the memory circuit 20, as shown in connection with the schematic of FIGURE 2, are available at pads 24. Connection between the pads 24 and the lead frame 26 (see FIGURE 3b) may be performed by wire bonding.
  • FIGURE 3b illustrates a lead frame 26 which is wire bonded to the memory circuit 20 shown in FIGURE 3a. The outline of the encapsulation packaging 13 and memory circuit 20 are shown for reference. In FIGURE 3b, the lead frame 26 is shown with the test points removed; the full lead frame prior to trimming is shown in greater detail in connection with FIGURE 4a.
  • Each subassembly 12 comprises a lead frame 26 having its leads 14 wire bonded to the pads 24 of the memory circuit 20.
  • the lead frame 26 is attached to the memory circuit 20 using a very thin adhesive, typically an epoxy, that provides mechanical support of the lead frame 26 during wire bonding and also provides a low thermal impedance path for heat flow from the semiconductor to the lead frame 26 which, in turn, conducts heat out of the HDMM 10 through a low thermal impedance path to convective surfaces for transfer into the ambient air.
  • a very thin adhesive typically an epoxy
  • the lead frame 26 uses a copper alloy material; however, most lead frame materials will also be good heat conductors.
  • a single lead frame configuration may be used in connection with any one of the subassemblies in the HDMM, regardless of its position in the stack, thereby reducing the complexity of manufacture.
  • the data input D of the memory circuit is coupled to a signal pad 28 which is electrically coupled via removable connections 30 to each of the leads 14 associated with pins D j -Dg.
  • a signal pad 28 which is electrically coupled via removable connections 30 to each of the leads 14 associated with pins D j -Dg.
  • all but one of the removable connections 30 are removed.
  • the lead frame 26 coupled to memory circuit 20a will have the removable connections 30 associated with leads D 2 -D 9 removed.
  • the lead frame 26 includes a signal pad 32 coupled to the data output Q of the memory circuit 20.
  • the signal pad 32 is coupled to the leads 14 associated with data outputs Q ⁇ -Q via removable connections 34. Again, for a particular subassembly level, the removable connections 34 for all but one of the leads 14 associated with Q j -Qg are removed.
  • memory circuit 20a has its data input pad D coupled to the D- ⁇ lead and has its data output pad Q coupled to the Q ⁇ lead.
  • the subassemblies 12 are marked either during or after encapsulation to identify the unique data input/output configuration.
  • the leads 14 are spaced on 0.025 inch (0.0635 cm) centers outside of the encapsulating package and configured as shown with holes 37 located to provide a three-dimensional interconnect via pins 16.
  • Each subassembly 12 should undergo a complete electrical test and subsequent burn-in after encapsulation.
  • FIGURE 4a illustrates the encapsulated memory circuit, showing the extended lead frame test points.
  • the lead frame 26 Prior to encapsulation, the lead frame 26 has extended leads 36 with test points 38.
  • the encapsulation process forms the subassemblies 12 with leads 14 still connected to extended leads 36.
  • the extended leads are encapsulated in the secondary package 40 with the test points 38 exposed.
  • the memory circuits may be easily tested.
  • FIGURE 4b illustrates a cutaway view showing the memory circuit 20 and lead frame 26 encapsulated within the package 13.
  • FIGURE 5 illustrates a bottom view of the bottom header 19a.
  • the bottom header includes the four capacitors 22a-d (shown in FIGURE 2) coupled between the pins associated with N cc and N ss .
  • FIGURE 6 illustrates an exploded view of the HDMM 10 to show the assembly of the various parts.
  • the subassemblies 12 are stacked, with each subassembly uniquely addressed using removable connections 30 and 34 such that each subassembly has a unique data input/output pin-out.
  • the bottom header is placed at the bottom of the stack of subassemblies, with the capacitors 22a-d disposed away from the subassemblies, (i.e., towards the circuit board) and the top header 19b is disposed above the stack of subassemblies 12.
  • the pins 16 are disposed through the vertically aligned leads 14 and the holes in the headers 19a-b.
  • a thin adhesive is used between each subassembly 12. Subsequent to placing the pins through the leads, the adhesive is cured and a reflow solder process is used on electrical joints using a high temperature solder to complete the assembly.
  • the bottom header 19a is fabricated from sheets of copper-clad high- temperature plastic that are subsequently drilled and etched or molded from high-temperature plastic and selectively copper-plated to provide the decoupling capacitor mounting pads and annular rings at each of the thirty-six holes.
  • the top header 19b is fabricated similarly, but without the capacitor mounting pads.
  • Each of the individual components may be packaged in embossed tape on reels to enhance material handling accuracy and to ease presentation to the assembly equipment.
  • the assembly process successively places the components onto the thirty-six individual pins that are cut from individual rolls of round wire.
  • the HDMM 10 may 1 be assembled in an inverted position such that the coined ends of the pins
  • each HDMM 10 may be electrically tested and placed
  • FIGUREs 7a-b illustrate a pin-out for a 1 M x 4-bit memory circuit
  • the 1 M x 4-bit memory circuit 42 comprises ten address
  • input/output DQ 2 is coupled to signal pad 48, input/output DQ 3 is coupled
  • signal pad 48 is coupled to leads 14 labeled DQ2(1)-DQ 2 (10), signal pad 50
  • 25 lead frame 44 will be uniquely identified by removing all but one of the
  • the lead frame 26 could provide sixteen data input leads and sixteen data output leads (or eighteen input/output leads using byte parity) using 1 M x 1-bit memory circuits.
  • the address range of the HDMM could be increased by using a higher density memory circuit (for example, a 4 Mbit x 1 memory circuit) and providing additional address leads or by using additional subassembly chip select signals.
  • the HDMM could be used with other memory technologies such as static RAM and flash memory circuits.

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
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Abstract

A high density memory module (10) includes a plurality of subassemblies (12), each subassembly (12) including a memory circuit (20), a lead frame (26) having a plurality of leads (14) coupled to the memory circuit (20) and encapsulating material (13) surrounding the memory circuit (20) and lead frame (26) such that the leads (14) extend outwardly from the encapsulating material (13). The memory module (10) is easily assembled and provides high density storage capability with convective heat transfer to reduce the temperature within the stack of subassemblies (12). A single lead frame (26) may be selectively addressed for use with each subassembly (12) within the memory module (10).

Description

DESCRIPTION
HIGH DENSITY MEMORY AND METHOD OF FORMING THE SAME
Technical Field This invention relates in general to integrated circuits, and more particularly to a high density memory module.
Background Art High speed digital processing systems often require large amounts of high speed memory. While mass memory devices, such as hard disks, are capable of storing large amounts of information, the speed associated with these devices is insufficient for many purposes. In many applications, speed considerations are satisfied by storing large amounts of information in semiconductor memory, such as dynamic random access memory (DRAM) and static random access memory (SRAM). Normally, semiconductor memory is packaged in DIPs (dual-inline packages), ZIPs (Zip-Zag Inline Packages), SOJs (Small Outline J-leaded), SIPs (single-inline packages), and SIMMs (single-inline memory module). In these packaging options, the package itself is many times the size of the semiconductor integrated circuit which performs the memory function. Applications which need a large amount of memory or provide user- upgradeable sockets for increasing the size of the memory often dedicate a large area on the circuit board for the memory chips. Currently, one megabit DRAMs are the industry standard memory circuits, with four megabit memory circuits now reaching price parity with the one megabit circuits. While board space is reduced by the improved chip densities, the need for increased memory generally outpaces the speed with which memory circuit densities are increased. A prior art interim solution to chip densities has been "piggy-backing" DIPs such that a stack of memory circuits are interconnected to emulate a higher density memory circuit. Piggy-backing has resulted in several problems and is seldom used anymore. A more modern solution is to interconnect a stack of memory circuits which are not contained in their typical package thereby effecting a greater density. An example of this approach is "3-D Memory Multichip Modules" from Texas Instruments. Present implementations of this approach present significant problems. First, the stacked memory circuits suffer from thermal problems, particularly affecting those memory circuits in the middle of the stack where the heat is not adequately dissipated. Second, the complexity of manufacturing the stacked memory circuits results in a relatively high cost in comparison with other packaging options. Third, testing of the memory circuits is difficult.
Disclosure of Invention According to the present invention, a high density memory module and method of forming the same is provided. The memory module has safe thermal characteristics, high testability, and may be fabricated using uncomplicated procedures. The memory module comprises a plurality of memory subassemblies, wherein each subassembly includes a memory circuit, a lead frame having a plurality of leads coupled to the memory circuit, and encapsulating material surrounding the memory circuit and the lead frame, such that the leads extend outwardly from the encapsulating material to allow convective heat transfer. Connectors couple the respective leads of the memory subassemblies outside the encapsulating material to electrically couple the memory circuits. Advantageously, the leads extend outwardly from the encapsulating material such that each of the memory circuits may dissipate heat by conductive heat transfer through the leads to a convective surface. The convective surface area can be adjusted for optimum heat transfer by adjusting the length of the lead outside the encapsulating material. Further, packaging of the memory circuit by the encapsulating material may be performed such that the leads may be used for testing prior to final assembly. In preferred embodiments, each lead frame has an identical layout such that predefined portions of the lead frame may be removed to provide a unique circuit configuration corresponding to the position of the memory circuit in the stack. The use of a single lead frame layout greatly simplifies the construction of the memory module.
Brief Description of Drawings Reference is now made to the following descriptions taken in conjunction with the accompanying drawings, in which: FIGURE la illustrates a perspective view of the high density memory module (HDMM); FIGURE lb illustrates a pin-out for the HDMM of FIGURE la; FIGURE 2 illustrates a schematic representation of the high density memory module ; FIGURE 3a illustrates a top view of a 1 M x 1 DRAM circuit showing the interconnection pads; FIGURE 3b illustrates a top view of a lead frame; FIGURE 4a illustrates a top view of the encapsulated RAM prior to assembly, showing the lead frame test points; FIGURE 4b illustrates an encapsulated DRAM subassembly prior to final assembly with cutaway views of the memory circuit and lead frame; FIGURE 5 illustrates a bottom perspective view of the bottom header of the memory module; FIGURE 6 illustrates an exploded view of the memory module; FIGURE 7a illustrates a top view of a 1 M x 4 DRAM circuit showing the interconnection pads; and FIGURE 7b illustrates a top view of a lead frame for a 1 M x 40-bit HDMM.
Best Mode for Carrying Out the Invention In referring to FIGUREs 1-7 of the drawings, like numerals are used for like and corresponding parts of the various drawings. FIGURE 1 illustrates a perspective view of a high density memory module (HDMM). The HDMM 10 comprises a plurality of stacked subassemblies 12 having protruding leads 14. Pins 16 are positioned through respective aligned leads 14. The pins 16 terminate in ends 18 which may be attached directly to a circuit board or inserted into a socket which is attached to a circuit board. A bottom header 19a and top header 19b are positioned at the bottom and top, respectively, of the HDMM 10. Each subassembly 12 includes a memory circuit coupled to a lead frame which has been encapsulated in a dielectric packaging material 13, with the leads 14 protruding from the packaging material. The lead frames are described in greater detail in connection with FIGURE 3b. Pins 16 provide electrical connections in the third (vertical) dimension to distribute the appropriate signals to multiple memory circuits. The subassemblies 12 may be configured in groups of eight (or nine to include a parity bit) to form bytes of digital data. The number of stacked subassemblies may be increased or decreased in order to provide a desired word size or an alternative configuration. For purposes of illustration, the HDMM will be described in connection with a 1 Mbit x 9 dynamic random access memory module, although other configurations can be easily designed. In addition to distributing signals from the memory circuits, the lead frames also provide thermal management. Heat from the memory circuits is conducted to the exterior of the HDMM by leads 14, which are cooled by the ambient air. Using a memory circuit having dimensions of approximately 0.180 x 0.400 inches (.4572 x 1.016 cm), an HDMM 10 may be formed having dimensions of approximately 0.340 x 0.475 x 0.435 inches (.8636 x 1.2065 x 1.1049 cm) using a stack of nine subassemblies 12. The HDMM achieves a packaging density approaching the practical maximum possible as limited by the physical size of the silicon, the lead frame and the necessary encapsulation for environmental protection. Current one megabit memory circuits have dimensions of approximately .243 x .115 inches (.6172 x .2921 cm), which significantly reduces the size of the silicon and improvements in encapsulation techniques would reduce the size of the HDMM. FIGURE lb illustrates a pin-out of the HDMM 10. For the illustrated embodiment of a 1 Mbit x 9 DRAM module ten address pins (Aø-Ag), nine data inputs (Dj-Dg), and nine data outputs (Qj-Qg) are provided. CAS, RAS and W provide the control signals to read and write to the HDMM. Nss and Ncc provide the power to the HDMM. FIGURE 2 illustrates a schematic representation of the interconnections between the memory circuits and the pins of the HDMM 10. The pin numbers, referenced to the pin-out of FIGURE lb, are shown parenthetically. Nine one-megabit memory circuits 20, referred to individually as memory circuits 20a-20i, are used to form the HDMM 10. Address pins AQ-Agare coupled to respective inputs for each of the memory circuits 20a- 20i. Similarly, Ncc, Nss, RAS, CAS and W pins are coupled to respective inputs of the memory circuits 20a-20i. The data inputs Dj-Dg and data outputs Q^-Qg are coupled to the data inputs (D) and data outputs (Q) of respective memory chips 20a-20i. Hence, D^ is coupled to data input D of memory circuit 20a, D2 is coupled to data input D of memory circuit 20b, D3is coupled to data input D of memory circuit 20c, and so on. Similarly, j^ is coupled to data output Q of memory circuit 20a, 2is coupled to data output Q of memory circuit 20b, and Q3 is coupled to data output Q of memory circuit 20c. Thus, for any given address, nine bits of data may be either written to, or read from, the HDMM 10. Decoupling capacitors 22 a- d are coupled between Ncc and Nss. FIGURE 3a illustrates a top view of an exemplary memory circuit 20. Signals from the memory circuit 20, as shown in connection with the schematic of FIGURE 2, are available at pads 24. Connection between the pads 24 and the lead frame 26 (see FIGURE 3b) may be performed by wire bonding. FIGURE 3b illustrates a lead frame 26 which is wire bonded to the memory circuit 20 shown in FIGURE 3a. The outline of the encapsulation packaging 13 and memory circuit 20 are shown for reference. In FIGURE 3b, the lead frame 26 is shown with the test points removed; the full lead frame prior to trimming is shown in greater detail in connection with FIGURE 4a. Each subassembly 12 comprises a lead frame 26 having its leads 14 wire bonded to the pads 24 of the memory circuit 20. The lead frame 26 is attached to the memory circuit 20 using a very thin adhesive, typically an epoxy, that provides mechanical support of the lead frame 26 during wire bonding and also provides a low thermal impedance path for heat flow from the semiconductor to the lead frame 26 which, in turn, conducts heat out of the HDMM 10 through a low thermal impedance path to convective surfaces for transfer into the ambient air. Typically, the lead frame 26 uses a copper alloy material; however, most lead frame materials will also be good heat conductors. Importantly, a single lead frame configuration may be used in connection with any one of the subassemblies in the HDMM, regardless of its position in the stack, thereby reducing the complexity of manufacture. The data input D of the memory circuit is coupled to a signal pad 28 which is electrically coupled via removable connections 30 to each of the leads 14 associated with pins Dj-Dg. To configure the lead frame 26 for a particular subassembly level, all but one of the removable connections 30 are removed. For example, the lead frame 26 coupled to memory circuit 20a will have the removable connections 30 associated with leads D2-D9 removed. Similarly, the lead frame 26 includes a signal pad 32 coupled to the data output Q of the memory circuit 20. The signal pad 32 is coupled to the leads 14 associated with data outputs Q^-Q via removable connections 34. Again, for a particular subassembly level, the removable connections 34 for all but one of the leads 14 associated with Qj-Qg are removed. Thus, for memory circuit 20a, all removable connections 34 are removed except for the connector associated with the Q^ lead. Hence, memory circuit 20a has its data input pad D coupled to the D-^ lead and has its data output pad Q coupled to the Q^lead. The subassemblies 12 are marked either during or after encapsulation to identify the unique data input/output configuration. In the preferred embodiment, the leads 14 are spaced on 0.025 inch (0.0635 cm) centers outside of the encapsulating package and configured as shown with holes 37 located to provide a three-dimensional interconnect via pins 16. Each subassembly 12 should undergo a complete electrical test and subsequent burn-in after encapsulation. FIGURE 4a illustrates the encapsulated memory circuit, showing the extended lead frame test points. Prior to encapsulation, the lead frame 26 has extended leads 36 with test points 38. The encapsulation process forms the subassemblies 12 with leads 14 still connected to extended leads 36. The extended leads are encapsulated in the secondary package 40 with the test points 38 exposed. Hence, at this point in the fabrication process, the memory circuits may be easily tested. As shown in FIGURE 4b, the subassemblies 12 are separated from the secondary package 40 prior to assembly of the HDMM 10. FIGURE 4b illustrates a cutaway view showing the memory circuit 20 and lead frame 26 encapsulated within the package 13. FIGURE 5 illustrates a bottom view of the bottom header 19a. The bottom header includes the four capacitors 22a-d (shown in FIGURE 2) coupled between the pins associated with Ncc and Nss. FIGURE 6 illustrates an exploded view of the HDMM 10 to show the assembly of the various parts. The subassemblies 12 are stacked, with each subassembly uniquely addressed using removable connections 30 and 34 such that each subassembly has a unique data input/output pin-out. The bottom header is placed at the bottom of the stack of subassemblies, with the capacitors 22a-d disposed away from the subassemblies, (i.e., towards the circuit board) and the top header 19b is disposed above the stack of subassemblies 12. The pins 16 are disposed through the vertically aligned leads 14 and the holes in the headers 19a-b. A thin adhesive is used between each subassembly 12. Subsequent to placing the pins through the leads, the adhesive is cured and a reflow solder process is used on electrical joints using a high temperature solder to complete the assembly. In the preferred embodiment, the bottom header 19a is fabricated from sheets of copper-clad high- temperature plastic that are subsequently drilled and etched or molded from high-temperature plastic and selectively copper-plated to provide the decoupling capacitor mounting pads and annular rings at each of the thirty-six holes. The top header 19b is fabricated similarly, but without the capacitor mounting pads. Each of the individual components (headers 19a-b, unique subassemblies 12, and capacitors 22) may be packaged in embossed tape on reels to enhance material handling accuracy and to ease presentation to the assembly equipment. In the preferred embodiment, the assembly process successively places the components onto the thirty-six individual pins that are cut from individual rolls of round wire. The HDMM 10 may 1 be assembled in an inverted position such that the coined ends of the pins
2 may more easily align with the hole pattern of each subassembly 12 in the
3 stack.
4 After cleaning, each HDMM 10 may be electrically tested and placed
5 in a temperature-cycle burn-in oven for final conditioning.
6 FIGUREs 7a-b illustrate a pin-out for a 1 M x 4-bit memory circuit
7 and a lead frame configuration for implementing a 1 M x 40 bit memory,
8 respectively. The 1 M x 4-bit memory circuit 42 comprises ten address
9 lines (Aø-Ag), four data input/output signals (DQ1-DQ ), power signals (Ncc, l o Nss) and control signals (CAS, RAS, OE and W). li Each of the data input/Output signals of the memory circuit 42 is
12 coupled to an associated signal pad on the 1 megabit x 40 lead frame 44.
13 Hence, input output DO^of memory circuit 42 is coupled to signal pad 46,
14 input/output DQ2 is coupled to signal pad 48, input/output DQ3 is coupled
15 to signal pad 50 and input/output DQ4 is coupled to signal pad 52. Each of
16 the signal pads 46-52 are coupled to a respective set often leads 14. Signal
17 pad 46 is coupled to ten leads 14, labeled DQ1(1)-DQ1(10), via removable
18 connections 34 as described in connection with FIGURE 3b. Similarly,
19 signal pad 48 is coupled to leads 14 labeled DQ2(1)-DQ2(10), signal pad 50
20 is coupled to leads 14 labeled DQ3(1)-DQ3(10) and signal pad 52 is coupled
21 to leads 14 labeled DQ4(1)-D 4( 10). The remaining connections between
22 memory circuit 42 and lead frame 44 are the same as described in
23 connection with FIGURE 3b.
24 For each subassembly level of the 1 M x 40 HDMM, the associated
25 lead frame 44 will be uniquely identified by removing all but one of the
26 removable connections 34 for each set of leads DQ1-DQ4. For example, at
27 the first level, leads DQjd), DQ2(1), DQ3(1) and DQ4(1) will each be
28 coupled to their respective signal pads while the remaining leads will be
29 decoupled by removing removable connections 34. For a 1 M x 40 HDMM, 3 o ten levels of subassemblies will be needed.
31 While the previous embodiments described a 1 Mbyte DRAM module,
32 other configurations could be similarly designed. For example, for a 1 M x 16 bit HDMM, the lead frame 26 could provide sixteen data input leads and sixteen data output leads (or eighteen input/output leads using byte parity) using 1 M x 1-bit memory circuits. Further, the address range of the HDMM could be increased by using a higher density memory circuit (for example, a 4 Mbit x 1 memory circuit) and providing additional address leads or by using additional subassembly chip select signals. Further, the HDMM could be used with other memory technologies such as static RAM and flash memory circuits. Various changes, substitutions and alterations can be made herein without departing from the scope of the invention as defined by the appended claims.

Claims

l CLAIMS
2
3 1. A memory module (10) comprising a plurality of memory
4 subassemblies (12), each subassembly (12) comprising (i) a memory circuit
5 (20), (ii) a lead frame (26) having a plurality of thermally and electrically
6 conductive leads (14) with selected leads (14) electrically coupled to said
7 memory circuit (20) and non-selected leads (14) electrically isolated from
8 said memory circuit (20), and (iii) an encapsulating material (13)
9 surrounding said memory circuit (20) and a portion of lead frame (26) 0 wherein said leads (14) extend outwardly from said encapsulating material i (13), said memory module (10) further comprising electrical connectors (16) 2 coupled to portions of said leads (14) outside of said encapsulating material 3 (13), characterized in that: 4 each of said leads (14) provides conductive heat transfer from said 5 memory circuit (20) to an area outside said encapsulating material (13) and 6 convective heat transfer from the portions of said leads (14) extending 7 outside of said encapsulating material (13); and s at least one of said selected leads (14) is selectably coupled to said 9 memory circuit (20). 0 1 2. A memory module (10) comprising a lead frame (26), a memory 2 circuit (20) and an encapsulating material (13), said lead frame (26) 3 comprising (i) a plurality of first leads (14) electrically coupled to said memory circuit (20) and extending outside said encapsulating material 5 (13), (ii) a plurality of second leads (14) extending outside said 6 encapsulating material (13), and (iii) a plurality of conductive surfaces 7 (28,32) electrically coupled to said memory circuit (20) and completely 8 surrounded by said encapsulating material (13), characterized by: 9 said lead frame (26) further comprising removable connectors (30,34) 0 for selectively coupling said second leads (14) to said conductive surfaces i (28,32). 2 1 3. A method of forming a memory module (10), comprising the steps
2 of (i) providing a plurality of lead frames (26) containing leads (14), (ii)
3 electrically coupling a plurality of memory circuits (20) to respective lead
4 frames (26), (iii) adhering said memory circuits (20) to said respective lead
5 frames (26), (iv) encapsulating said coupled memory circuits (20) and
6 portions of said respective lead frames (26) to form memory subassemblies
7 (12) such that outer ends of leads (14) extend out from an encapsulating
8 material (13), and (v) electrically coupling said subassemblies (12) by
9 interconnecting said outer ends of leads (14), characterized by: 0 configuring a plurality of identical lead frames (26) in step (i) such i that each of said plurality of lead frames (26) provides a unique 2 input/output data path for the respective memory circuit (20). 3 4 4. A three-dimensional memory module (10) comprising (I) a 5 plurality of horizontally-oriented, vertically-stacked memory subassemblies 6 (12), each memory subassembly (12) comprising (i) a memory circuit (20) 7 comprising a plurality of bonding pads (24) for receiving data input signals, 8 address signals, control signals and power supply voltages, and for sending 9 data output signals, (ii) a lead frame (26) formed of thermally and o electrically conductive material comprising a plurality of outwardly 1 extending leads (14) wherein selected leads (14) are electrically coupled to 2 said pads (24) whereas non-selected leads (14) are electrically isolated from 3 said pads (24), (iii) a mechanical coupling element between said memory 4 circuit (20) and said lead frame (26), and (iv) a dielectric material (13) 5 surrounding and encapsulating said memory circuit (20) and a portion of 6 said lead frame (26) wherein the unencapsulated portion of said lead frame 7 (26) includes outer portions of leads (14), said outer portions of leads (14) 8 protruding from said dielectric material (13) and providing convective 9 surface areas to ambient air outside said dielectric material (13), wherein o said lead frames (26) are positioned so that said outer portions of leads (14) 1 are aligned in vertical columns, and (II) a plurality of separate, spaced 2 vertically-oriented electrical connectors (16) positioned outside said dielectric material (13) wherein each electrical connector (16) electrically couples the outer portion of each lead (14) in a single vertical column of leads (14) without electrically coupling the outer portion of any leads (14) outside said single vertical column, characterized in that: a thermal coupling element is between said memory circuit (20) and said lead frame (26); said lead frame (26) provides a low thermal impedance path that allows said memory circuit (20) to dissipate heat by conductive heat transfer through said thermal coupling element into said lead frame (26) within said dielectric material (13) and through said lead frame (26) within said dielectric material (13) to the convective surface areas of said outer portions of leads (14); said lead frames (26) are configured so that each data input pad (24) of each memory circuit (20) is the only data input pad (24) in the memory module (10) which is electrically coupled to a selected electrical connector (16), thereby providing each memory subassembly (12) with a unique data input configuration corresponding to the position of the memory subassembly (12) in the stack; and said lead frames (26) are configured so that each data output pad (24) of each memory circuit (20) is the only data output pad in the memory module (10) which is electrically coupled to a selected electrical connector (16), thereby providing each memory subassembly (12) with a unique data output configuration corresponding to the position of the memory subassembly (12) in the stack.
5. The memory module (10) of claim 4 wherein: said outer portions of leads (14) of each lead frame (26) have identical layouts, said dielectric materials (13) have identical layouts, and said memory subassemblies (12) are stacked adjacent to one another; said electrical connectors (16) are formed of thermally and electrically conductive metal, provide convective surface areas to said ambient air, and are electrically and thermally coupled to said vertical columns of leads (14); the entire surfaces of said outer portions of leads (14) and the entire surfaces of said electrical connectors ( 16) between the top and bottom of the stack are convective surface areas; and said lead frame (26) is formed with opposing major surfaces parallel to one another, said memory circuit (20) is disposed over said leads (14), said mechanical coupling element mechanically couples said memory circuit (20) to portions of said leads (14) beneath said memory circuit (20), said thermal coupling element thermally couples said memory circuit (20) to portions of said leads (14) beneath said memory circuit (20); and metalhc bonds electrically couple said pads (24) to said selected leads (14).
6. The memory module (10) of claim 4 wherein: said memory circuit (20) is disposed over said leads (14); said mechanical coupling element mechanically couples said memory circuit (20) to portions of said leads (14) beneath said memory circuit (20); said thermal coupling element thermally couples said memory circuit (20) to portions of said leads (14) beneath said memory circuit (20); and metallic bonds electrically couple said pads (24) to said selected leads (14).
7. The memory module ( 10 ) of claim 6 wherein: said lead frame (26) consists of said leads (14); said leads (14) have flat and parallel top and bottom surfaces within said dielectric material (13); said memory circuit (20) is formed with a flat bottom surface facing said leads (14) and opposite said pads (24); and said mechanical coupling element adhesively connects the bottom surface of said memory circuit (20) to the top surfaces of said leads (14) therebeneath.
8. The memory module (10) of claim 4 wherein all low thermal impedance paths between said memory circuit (20) and said ambient air must include said thermal coupling element and said lead frame (26).
9. The memory module (10) of claim 4 wherein: said memory circuit (20) and said lead frame (26) are the only thermally conductive materials in contact with said thermal coupling element; and said lead frame (26) is the only thermally conductive material both within and in contact with said dielectric material (13).
10. The memory module (10) of claim 4 wherein said mechanical and thermal coupling elements are a single adhesive material in full surface contact with one surface of said memory circuit (20).
11. The memory module (10) of claim 4 wherein: all electrical interconnections between said pads (24) and circuitry outside said dielectric material (13) must include said selected leads (14); in each of said memory subassemblies (12), excluding said power supply pads (24), each of said pads (24) is coupled to a single selected lead (14) and each of said selected leads is coupled to a single pad (24); said memory subassemblies (12) have identical power supply, control signal and address signal configurations, and said electrical connectors (16) connect all power supply voltages, control signals and address signals in common among said memory circuits (20); some but not all of said selected leads (14) in a given memory assembly (12) include a removable connection surrounded by said encapsulating material (13); and each of said non-selected leads (14) in a given memory subassembly (12) is electrically coupled to a single electrical connector (16) which is electrically coupled to a single pad (24) on a single memory circuit (20) in another memory subassembly (12), said single pad (24) functioning as at least one of said data input pad (24) or said data output pad (24).
12. The memory module (10) of claim 4 wherein: said unique data input and data output configurations for said memory circuit (20) are provided by several opened connections on the encapsulated portion of said lead frame (26); each non-selected lead (14) is rendered electrically isolated from said pads (14) by a single opened connection; said data input pad (24) is electrically coupled to a single selected lead (14) which includes a removable connection (30); said data output pad (24) is electrically coupled to a single selected lead (14) which includes a removable connection (34); and each of said lead frames (26) has a uniquely positioned removable connection (30,34) included in one but not all of said selected leads (14).
PCT/US1993/006315 1992-07-07 1993-07-02 High density memory and method of forming the same WO1994001887A1 (en)

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Cited By (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0700086A3 (en) * 1994-08-29 1997-08-20 Analog Devices Inc Integrated circuit package with improved heat dissipation
US5675180A (en) * 1994-06-23 1997-10-07 Cubic Memory, Inc. Vertical interconnect process for silicon segments
US5891761A (en) * 1994-06-23 1999-04-06 Cubic Memory, Inc. Method for forming vertical interconnect process for silicon segments with thermally conductive epoxy preform
US6080596A (en) * 1994-06-23 2000-06-27 Cubic Memory Inc. Method for forming vertical interconnect process for silicon segments with dielectric isolation
US6124633A (en) * 1994-06-23 2000-09-26 Cubic Memory Vertical interconnect process for silicon segments with thermally conductive epoxy preform
EP1067602A1 (en) * 1999-07-07 2001-01-10 EEMS Italia S.p.a. Un-packaged or semi-packaged electrically tested electronic semiconductor device free from infantile mortality and process for manufacture thereof
US6255726B1 (en) 1994-06-23 2001-07-03 Cubic Memory, Inc. Vertical interconnect process for silicon segments with dielectric isolation
US6486528B1 (en) 1994-06-23 2002-11-26 Vertical Circuits, Inc. Silicon segment programming apparatus and three terminal fuse configuration
EP1343169A2 (en) 2002-03-07 2003-09-10 Hewlett-Packard Company Memory Systems

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5028986A (en) * 1987-12-28 1991-07-02 Hitachi, Ltd. Semiconductor device and semiconductor module with a plurality of stacked semiconductor devices

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5028986A (en) * 1987-12-28 1991-07-02 Hitachi, Ltd. Semiconductor device and semiconductor module with a plurality of stacked semiconductor devices

Cited By (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5675180A (en) * 1994-06-23 1997-10-07 Cubic Memory, Inc. Vertical interconnect process for silicon segments
US5837566A (en) * 1994-06-23 1998-11-17 Cubic Memory, Inc. Vertical interconnect process for silicon segments
US5891761A (en) * 1994-06-23 1999-04-06 Cubic Memory, Inc. Method for forming vertical interconnect process for silicon segments with thermally conductive epoxy preform
US6080596A (en) * 1994-06-23 2000-06-27 Cubic Memory Inc. Method for forming vertical interconnect process for silicon segments with dielectric isolation
US6124633A (en) * 1994-06-23 2000-09-26 Cubic Memory Vertical interconnect process for silicon segments with thermally conductive epoxy preform
US6188126B1 (en) 1994-06-23 2001-02-13 Cubic Memory Inc. Vertical interconnect process for silicon segments
US6255726B1 (en) 1994-06-23 2001-07-03 Cubic Memory, Inc. Vertical interconnect process for silicon segments with dielectric isolation
US6486528B1 (en) 1994-06-23 2002-11-26 Vertical Circuits, Inc. Silicon segment programming apparatus and three terminal fuse configuration
EP0700086A3 (en) * 1994-08-29 1997-08-20 Analog Devices Inc Integrated circuit package with improved heat dissipation
EP1067602A1 (en) * 1999-07-07 2001-01-10 EEMS Italia S.p.a. Un-packaged or semi-packaged electrically tested electronic semiconductor device free from infantile mortality and process for manufacture thereof
EP1343169A2 (en) 2002-03-07 2003-09-10 Hewlett-Packard Company Memory Systems
EP1343169A3 (en) * 2002-03-07 2004-03-24 Hewlett-Packard Company Memory Systems

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