JPH08321486A - 金属膜のパターン形成方法 - Google Patents

金属膜のパターン形成方法

Info

Publication number
JPH08321486A
JPH08321486A JP7125119A JP12511995A JPH08321486A JP H08321486 A JPH08321486 A JP H08321486A JP 7125119 A JP7125119 A JP 7125119A JP 12511995 A JP12511995 A JP 12511995A JP H08321486 A JPH08321486 A JP H08321486A
Authority
JP
Japan
Prior art keywords
film
plasma
metal film
substrate
pattern
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP7125119A
Other languages
English (en)
Japanese (ja)
Inventor
Toshiharu Yanagida
敏治 柳田
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Sony Corp
Original Assignee
Sony Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Sony Corp filed Critical Sony Corp
Priority to JP7125119A priority Critical patent/JPH08321486A/ja
Priority to TW085104857A priority patent/TW312812B/zh
Priority to US08/650,271 priority patent/US5888892A/en
Priority to KR1019960017378A priority patent/KR100345622B1/ko
Priority to CA002177244A priority patent/CA2177244C/en
Publication of JPH08321486A publication Critical patent/JPH08321486A/ja
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
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    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L24/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
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    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/027—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
    • H01L21/0271—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising organic layers
    • H01L21/0272—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising organic layers for lift-off processes
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    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76877—Filling of holes, grooves or trenches, e.g. vias, with conductive material
    • H01L21/7688—Filling of holes, grooves or trenches, e.g. vias, with conductive material by deposition over sacrificial masking layer, e.g. lift-off
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    • H01L2224/03—Manufacturing methods
    • H01L2224/0347—Manufacturing methods using a lift-off mask
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    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/0401—Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
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    • H01L2224/05599—Material
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    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13099—Material
    • H01L2224/131—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/13138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/13144—Gold [Au] as principal constituent
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    • H01L2924/05042—Si3N4
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    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/14—Integrated circuits
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    • H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
    • H01L2924/1901—Structure
    • H01L2924/1904—Component type
    • H01L2924/19041—Component type being a capacitor
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S438/00—Semiconductor device manufacturing: process
    • Y10S438/942—Masking
    • Y10S438/948—Radiation resist
    • Y10S438/951—Lift-off

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Power Engineering (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Manufacturing & Machinery (AREA)
  • General Physics & Mathematics (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Drying Of Semiconductors (AREA)
  • Electrodes Of Semiconductors (AREA)
  • Exposure Of Semiconductors, Excluding Electron Or Ion Beam Exposure (AREA)
  • Photosensitive Polymer And Photoresist Processing (AREA)
JP7125119A 1995-05-24 1995-05-24 金属膜のパターン形成方法 Pending JPH08321486A (ja)

Priority Applications (5)

Application Number Priority Date Filing Date Title
JP7125119A JPH08321486A (ja) 1995-05-24 1995-05-24 金属膜のパターン形成方法
TW085104857A TW312812B (enExample) 1995-05-24 1996-04-23
US08/650,271 US5888892A (en) 1995-05-24 1996-05-22 Metal layer pattern forming method
KR1019960017378A KR100345622B1 (ko) 1995-05-24 1996-05-22 금속막의패턴형성방법
CA002177244A CA2177244C (en) 1995-05-24 1996-05-23 Metal layer pattern forming method

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP7125119A JPH08321486A (ja) 1995-05-24 1995-05-24 金属膜のパターン形成方法

Publications (1)

Publication Number Publication Date
JPH08321486A true JPH08321486A (ja) 1996-12-03

Family

ID=14902323

Family Applications (1)

Application Number Title Priority Date Filing Date
JP7125119A Pending JPH08321486A (ja) 1995-05-24 1995-05-24 金属膜のパターン形成方法

Country Status (5)

Country Link
US (1) US5888892A (enExample)
JP (1) JPH08321486A (enExample)
KR (1) KR100345622B1 (enExample)
CA (1) CA2177244C (enExample)
TW (1) TW312812B (enExample)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH10284497A (ja) * 1997-04-08 1998-10-23 Sony Corp 半導体装置の製造方法
US6214717B1 (en) * 1998-11-16 2001-04-10 Taiwan Semiconductor Manufacturing Company Method for adding plasma treatment on bond pad to prevent bond pad staining problems
CN117791297A (zh) * 2023-12-26 2024-03-29 武汉敏芯半导体股份有限公司 半导体激光器的电极的制备方法及电极

Families Citing this family (16)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
GB2352084B (en) * 1999-07-13 2002-11-13 Simage Oy Forming contacts on semiconductor substrates for radiation detectors and imaging devices
US6410922B1 (en) 1995-11-29 2002-06-25 Konstantinos Evangelos Spartiotis Forming contacts on semiconductor substrates for radiation detectors and imaging devices
US20020158207A1 (en) * 1996-11-26 2002-10-31 Simage, Oy. Forming contacts on semiconductor substrates for radiation detectors and imaging devices
US6440836B1 (en) * 1999-03-16 2002-08-27 Industrial Technology Research Institute Method for forming solder bumps on flip chips and devices formed
US6420252B1 (en) * 2000-05-10 2002-07-16 Emcore Corporation Methods of forming robust metal contacts on compound semiconductors
US6586323B1 (en) * 2000-09-18 2003-07-01 Taiwan Semiconductor Manufacturing Company Method for dual-layer polyimide processing on bumping technology
US6375062B1 (en) * 2000-11-06 2002-04-23 Delphi Technologies, Inc. Surface bumping method and structure formed thereby
US6372545B1 (en) 2001-03-22 2002-04-16 Taiwan Semiconductor Manufacturing Company Method for under bump metal patterning of bumping process
US6784089B2 (en) * 2003-01-13 2004-08-31 Aptos Corporation Flat-top bumping structure and preparation method
KR100510543B1 (ko) * 2003-08-21 2005-08-26 삼성전자주식회사 표면 결함이 제거된 범프 형성 방법
KR101112538B1 (ko) * 2004-07-27 2012-03-13 삼성전자주식회사 박막 트랜지스터 표시판 및 그 제조 방법
US9929080B2 (en) * 2004-11-15 2018-03-27 Intel Corporation Forming a stress compensation layer and structures formed thereby
US7713860B2 (en) * 2007-10-13 2010-05-11 Wan-Ling Yu Method of forming metallic bump on I/O pad
JP2010205829A (ja) * 2009-03-02 2010-09-16 Mitsubishi Electric Corp 半導体発光素子及びその製造方法
CN111554581A (zh) * 2020-04-07 2020-08-18 厦门通富微电子有限公司 一种导电柱的形成工艺及封装体
CN111668184B (zh) * 2020-07-14 2022-02-01 甬矽电子(宁波)股份有限公司 引线框制作方法和引线框结构

Family Cites Families (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4933303A (en) * 1989-07-25 1990-06-12 Standard Microsystems Corporation Method of making self-aligned tungsten interconnection in an integrated circuit
EP0469216B1 (en) * 1990-07-31 1994-12-07 International Business Machines Corporation Method of forming metal contact pads and terminals on semiconductor chips
JP3294411B2 (ja) * 1993-12-28 2002-06-24 富士通株式会社 半導体装置の製造方法
US5393697A (en) * 1994-05-06 1995-02-28 Industrial Technology Research Institute Composite bump structure and methods of fabrication
US5486483A (en) * 1994-09-27 1996-01-23 Trw Inc. Method of forming closely spaced metal electrodes in a semiconductor device

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH10284497A (ja) * 1997-04-08 1998-10-23 Sony Corp 半導体装置の製造方法
US6214717B1 (en) * 1998-11-16 2001-04-10 Taiwan Semiconductor Manufacturing Company Method for adding plasma treatment on bond pad to prevent bond pad staining problems
CN117791297A (zh) * 2023-12-26 2024-03-29 武汉敏芯半导体股份有限公司 半导体激光器的电极的制备方法及电极

Also Published As

Publication number Publication date
US5888892A (en) 1999-03-30
CA2177244A1 (en) 1996-11-25
TW312812B (enExample) 1997-08-11
KR100345622B1 (ko) 2002-11-30
CA2177244C (en) 2007-10-09
KR960042972A (ko) 1996-12-21

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