TW312812B - - Google Patents
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- Publication number
- TW312812B TW312812B TW085104857A TW85104857A TW312812B TW 312812 B TW312812 B TW 312812B TW 085104857 A TW085104857 A TW 085104857A TW 85104857 A TW85104857 A TW 85104857A TW 312812 B TW312812 B TW 312812B
- Authority
- TW
- Taiwan
- Prior art keywords
- film
- plasma
- substrate
- pattern
- metal film
- Prior art date
Links
- 239000000758 substrate Substances 0.000 claims description 47
- 238000000034 method Methods 0.000 claims description 38
- 229910052751 metal Inorganic materials 0.000 claims description 33
- 239000002184 metal Substances 0.000 claims description 33
- 229920002120 photoresistant polymer Polymers 0.000 claims description 23
- 230000008569 process Effects 0.000 claims description 15
- 239000010931 gold Substances 0.000 claims description 13
- 229910052737 gold Inorganic materials 0.000 claims description 12
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 claims description 11
- 238000009616 inductively coupled plasma Methods 0.000 claims description 10
- 238000000059 patterning Methods 0.000 claims description 7
- 239000004065 semiconductor Substances 0.000 claims description 7
- 238000012546 transfer Methods 0.000 claims description 5
- BSYNRYMUTXBXSQ-UHFFFAOYSA-N Aspirin Chemical compound CC(=O)OC1=CC=CC=C1C(O)=O BSYNRYMUTXBXSQ-UHFFFAOYSA-N 0.000 claims description 3
- 230000005611 electricity Effects 0.000 claims description 3
- GMCGCPYXMNXJQM-UHFFFAOYSA-N gold thorium Chemical compound [Au][Th] GMCGCPYXMNXJQM-UHFFFAOYSA-N 0.000 claims 1
- 239000010408 film Substances 0.000 description 128
- 238000012545 processing Methods 0.000 description 25
- 230000015572 biosynthetic process Effects 0.000 description 18
- 230000007261 regionalization Effects 0.000 description 9
- 239000010410 layer Substances 0.000 description 8
- 150000002500 ions Chemical class 0.000 description 7
- 238000002161 passivation Methods 0.000 description 6
- 229910000679 solder Inorganic materials 0.000 description 6
- 230000008878 coupling Effects 0.000 description 5
- 238000010168 coupling process Methods 0.000 description 5
- 238000005859 coupling reaction Methods 0.000 description 5
- 230000006866 deterioration Effects 0.000 description 5
- 239000007789 gas Substances 0.000 description 5
- 239000007788 liquid Substances 0.000 description 5
- 238000002203 pretreatment Methods 0.000 description 5
- 238000005507 spraying Methods 0.000 description 4
- 230000001939 inductive effect Effects 0.000 description 3
- 238000004519 manufacturing process Methods 0.000 description 3
- 239000012528 membrane Substances 0.000 description 3
- 238000009832 plasma treatment Methods 0.000 description 3
- 230000001681 protective effect Effects 0.000 description 3
- 230000002829 reductive effect Effects 0.000 description 3
- 239000002344 surface layer Substances 0.000 description 3
- 239000003990 capacitor Substances 0.000 description 2
- 229910052802 copper Inorganic materials 0.000 description 2
- 239000010949 copper Substances 0.000 description 2
- 238000009792 diffusion process Methods 0.000 description 2
- 238000005516 engineering process Methods 0.000 description 2
- 230000002265 prevention Effects 0.000 description 2
- 230000003068 static effect Effects 0.000 description 2
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 1
- UFHFLCQGNIYNRP-UHFFFAOYSA-N Hydrogen Chemical compound [H][H] UFHFLCQGNIYNRP-UHFFFAOYSA-N 0.000 description 1
- 238000010521 absorption reaction Methods 0.000 description 1
- 229910052782 aluminium Inorganic materials 0.000 description 1
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 1
- 230000008859 change Effects 0.000 description 1
- 229910052804 chromium Inorganic materials 0.000 description 1
- 239000011651 chromium Substances 0.000 description 1
- 238000001816 cooling Methods 0.000 description 1
- 238000005260 corrosion Methods 0.000 description 1
- 230000002950 deficient Effects 0.000 description 1
- 238000013461 design Methods 0.000 description 1
- 239000003989 dielectric material Substances 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 230000007613 environmental effect Effects 0.000 description 1
- RZDQHXVLPYMFLM-UHFFFAOYSA-N gold tantalum Chemical compound [Ta].[Ta].[Ta].[Au] RZDQHXVLPYMFLM-UHFFFAOYSA-N 0.000 description 1
- 239000001257 hydrogen Substances 0.000 description 1
- 229910052739 hydrogen Inorganic materials 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 230000000670 limiting effect Effects 0.000 description 1
- 238000001459 lithography Methods 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 230000007246 mechanism Effects 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 230000003647 oxidation Effects 0.000 description 1
- 238000007254 oxidation reaction Methods 0.000 description 1
- 230000036961 partial effect Effects 0.000 description 1
- 239000002245 particle Substances 0.000 description 1
- 238000007781 pre-processing Methods 0.000 description 1
- HNJBEVLQSNELDL-UHFFFAOYSA-N pyrrolidin-2-one Chemical compound O=C1CCCN1 HNJBEVLQSNELDL-UHFFFAOYSA-N 0.000 description 1
- 239000010453 quartz Substances 0.000 description 1
- 239000003507 refrigerant Substances 0.000 description 1
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N silicon dioxide Inorganic materials O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 1
- 239000002002 slurry Substances 0.000 description 1
- 238000005476 soldering Methods 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
- 239000013589 supplement Substances 0.000 description 1
- 238000007751 thermal spraying Methods 0.000 description 1
- 239000010409 thin film Substances 0.000 description 1
- 238000013519 translation Methods 0.000 description 1
- 239000002699 waste material Substances 0.000 description 1
- 238000001039 wet etching Methods 0.000 description 1
- 238000004804 winding Methods 0.000 description 1
Classifications
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- H—ELECTRICITY
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- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
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- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
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- H01L21/76877—Filling of holes, grooves or trenches, e.g. vias, with conductive material
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- H01L2224/131—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
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- Y10S438/00—Semiconductor device manufacturing: process
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- Y10S438/948—Radiation resist
- Y10S438/951—Lift-off
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- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Power Engineering (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Manufacturing & Machinery (AREA)
- General Physics & Mathematics (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
- Drying Of Semiconductors (AREA)
- Photosensitive Polymer And Photoresist Processing (AREA)
- Electrodes Of Semiconductors (AREA)
- Exposure Of Semiconductors, Excluding Electron Or Ion Beam Exposure (AREA)
Description
經濟部中央標準局貝工消费合作社印製 A7 ______B7____五、發明説明(1 ) 〔產業上之利用領域〕 本發明係關於一種金屬膜之圖案形成方法’係在半導 體基板的表面上形成由金屬構成之凸起’與形成於印刷電 路基板表面上之電極作面接合之反裝晶片(flip-chip) Ic之製造過程的一部分(構成突起之基底)之金靥膜之 圖案形成法。 〔先前之技術〕 爲了使電子機器之小型化更進一步地發展,如何提高 構件實裝密度成爲重要的關鍵。特別是關於半導體I C, 爲了代替以往之包裝實裝(package mounting) ’’很盛 行地進行利用反裝晶片之高密度實裝技術的開發。 在反裝晶片實裝法中,有金(A u )接觸柱凸出法或 錫焊球法等幾種手法,惟不管任何方式,爲了提高密著性 或相互擴散防止等目的,在半導體I C之電極襯墊與凸出 材料間,使用可變金屬。在使用錫焊球之場合,由於該可 變金屬具有決定凸出之成形形狀之作用,故又稱爲BL Μ (Ball Limitting Meta 1 )。對於錫焊球之B L Μ膜構 造,最普遍者爲C r,Cu,Au之三層構造。其中,下 層之C r層係作爲與電極襯墊之密著層、c u膜係作爲錫 焊之擴散防止層、而上層之A u金靥膜係作爲c u之氧化. 防止膜之作用。B LM膜之圖案形成方法中,雖然有利用 藥液之濕蝕刻法,惟在此情況下有作業性或廢液處理等環 保問題或加工精度不良等缺點》 本紙張尺度適用中國國家標準(CNS ) A4規格(210X297公釐) 一 -4 - (請先閲讀背面之注意事項再填寫本頁) 經濟部中央標準局貝工消費合作社印裝 312812 A7 _B7_五、發明説明(2 ) 因此,作爲B LM膜之圖案形成方法,在施加照相抗 蝕劑膜後,然後進行剝離之剝離過程之方法也被研究。此 時,B LM膜之成膜通常係以噴鍍裝置來進行,惟因爲有 成膜至基底的抗蝕圖案之側壁面之傾向,在剝離時,因爲 保護膜剝離液無法浸透,所以很難除去不要部分之B LM 膜。因此,爲提高剝離作業之剝離性,必須控制照相抗蝕 膜之開口端面形成外伸狀之形狀。此抗蝕膜形狀控制之方 法中,雖然有利用石版印刷之辦法來實現之方法,然而有 招致增加過程數量之缺點,所以若能在噴鍍B LM膜過程 之前處理過程中,利用通常實施之離子照射處理,同時進 行抗蝕圖案之形狀控制則甚爲理想。 以往,爲了實施金屬膜成膜前之電漿照射處理,一般 使用如第2圖所示之平行平板型電漿處理裝置。第2圖之 電漿處理裝置1,係在抽真空之電漿處理室2內配置放置 被處理基板3之階台(陰極板)4,在其相對位置上,配 置陽極板5,介由耦合電容器7將高周波電源6連接至階 台4。 又,在以照相抗蝕劑膜之剝離來進行金屬之圖案成形 之情況,憑藉此電漿照射處理,藉由使基底的抗蝕圖案熱 變質及離子照射,使其變形成爲外伸狀,在成膜於此上之 BLM膜端部製成斷隙(反過來利用噴鍍膜之階台覆蓋不 良處),由此處使抗蝕剝離液浸透,以去除不要部分之 BLM膜,完成圖案成形。 然而,爲了安定地實施該電漿照射之基底抗蝕圖案之 本紙張尺度適用t國國家標準(CNS)A4規格(210X297公釐) (請先閲讀背面之注意事項再填寫本頁) ~ 5 - A7 B7 五、發明説明(3 ) 形狀控制,抗蝕膜厚之選擇也相當重要,若使用如以往之 約1 /zm之抗蝕圖案時,由電漿照射而受到熱變質之區域 不止於抗蝕表面層而達到基底表面,抗蝕膜成爲燒著於基 底之狀態,而產生在後工程中之剝離時,抗蝕圖案之剝離 去除困難之問題。 爲了避免此問題,雖可考慮減少電漿照射量,惟若減 少電漿處理量時,抗蝕圖案之開口端部之形狀變化將不充 分,因爲B LM膜之成膜轉移入抗蝕圖案之側壁部,所以 抗蝕剝離液無法完全浸透,因此仍然無法憑藉剝離來完成 圖案成形》 又,在以往之金靥膜成膜前處理中,因爲沒有特別注 意處理中之晶圓的溫度上昇,故在通常之標準條件下,實 施電漿處理時之基板表面的最髙溫度約達到2 0 0 °C〜 2 5 0 °C » '若對施予抗蝕之圖案形成之試料晶圓,仍實施此種處 理時,抗蝕圖案之開口端將形成向斜上方突出之形狀變形 » (參照第6圖(b)) » 經濟部中央標準局員工消費合作社印製 ----------^ 衣-- (請先閱讀背面之注意事項再填寫本頁) 這是由於抗蝕膜表面急劇地受到過多的熱能,破壞了 原來的分子構造而發生縮小體積,該表面應力大於因熱膨 張而產生之抗蝕膜端欲往橫方向伸展之力量的現象。 此時,因爲抗蝕膜開口部之外伸不充分,致亦有噴鍍 粒子轉移入圖案側壁部而發生B LM膜之成膜,在後工程 之剝離處理時,剝離液無法浸透而無法完成圖案之形成。 又,亦產生抗蝕膜炭化而燒著於基底.之問題。(參照圖6 本紙張尺度適用中國國家標準(CNS ) Α4規格(210Χ297公釐) -6 - Λ> -»μ- ? 声 JL -» 補充 第85104857號專利案 A7 中文説明窨埯译頁 民國86年6月修正 五、發明说明(4 ) (d ) ) ·' 〔本發明所欲解決之課題〕 因此,本發明之課題爲提供在反裝晶片(flip-chip )I C之等之球突出形成之時之多層金屬膜(B LM ( <- ♦
Ball LimittingMetal )膜)形成工程之前處理工程中,容 易進行抗蝕膜之形成控制且不影響下層之金屬膜之圖案形 成方法· 〔用以解決課題之手段〕 . 經濟部中央揉準局負工消费合作杜印製 {請先聞讀背面之注意事項再填寫本頁) 爲解決此問題*在申請專利範園第1項之金靥膜之圖 案形成法中,對於依序將電極祺墊、表面保護膜、照相抗 蝕膜層叠稹於半導髖φ板上之被處理基板,實施電漿照射 處理,叠積金屬膜層,進行剝離處理之金屬膜之圖案形成 法.,係使照相抗蝕膜厚度形成爲金屬膜厚度之2倍以上· 申請專利範圍第2項之發明*係如申請專利範圍第1 項所述之金饜膜之圖案形成法中,將被處理基板之表面最 高’到達溫度設定爲1 0』eC〜1 5 0 eC之處理條件· 申請專利範圍第3項之發明,係如申請專利範園第1 項所述之金靥膜之圖案之形成法,其特徵係使用具有可得 到 I C P ( Inductively Coupled Plasma) , T C P ( Transfer Coupled Plasma) · E C R ( Electron Coupled Resonance),媒旋波(helicon wave)-電续等 ,電漿密度在1 x 1 OMcm-3至1 x 1 014cm·3之間 本紙張尺度通用中國困家標準(CNS ) A4規格(210X297公釐) 7 經濟部中央標準局貝工消费合作社印製 312812五、發明説明(5 ) 之高密度電漿源之電將處理裝置。 〔作用〕 對於申請專利範圍第1項之發明’因照相抗蝕膜具有 比金屬膜更厚之厚度’故照相抗触膜側壁幾乎無金屬膜 形成,又因受熱變質影響之領域不會達到下層表面’故在 剝離時容易剝離不要部分之金靥膜。 對於申請專利範圍第2項之·發明’可適度改良照相抗 蝕膜之表面性質,不會產生過多之熱變質。 對於申請專利範圍第3項之發明’ 0®梁處理裝置之 電將源,係使用可以得到1 c P ( Inductively Coupled Plasma) * T C P ( Transfer Coupled Plasma) ’ E C R ( Electron Coupled Resonance) ’ 螺旋波( helicon wave)電獎.等’電楽密度在1 x 1 〇 llc m_3至 1 x 1 0 14c m-3之間之高密度電漿源之電將處理裝置, 所以可以分別獨立地控制基板偏壓電壓和電漿電力。 〔實施例〕 以下,參照第1圖至第4圖來說明關於本發明之金屬 膜之圖案形成法。 實施例1 本實施例係將本發明應用於錫焊球突出形成時之由金 屬膜構成之B LM (Ball Limitting Metal)膜之圖案形 A7 (請先閱讀背面之注意事項再填寫本頁) 訂 -! 本紙浪尺度適用中國國家標準(CNS > A4規格(210 X 297公釐) A7 B7 經濟部中央標準局員工消費合作社印裝 五、 發明说明 (6 ) 1 1 成 〇 1 1 本 實 施 例 中 tt.t. 做 爲 樣 品 使 用 之 被 處 理 基 板 3 ( 晶 圓 ) 1 I 係 如 第 1 ( a ) 圖 所 示 在 半 導 體 rLSL 基 板 8 之 鋁 電 極 襯 塾 9 1 | 上 形 成 聚 亞 胺 或 氮 化 矽 膜 等 鈍 化 膜 ( 表 面 保 護 膜 ) 1 0 請 先 明 1 1 I 連 接 孔 1 1 以 規 定 之 尺 寸 被 穿 孔 > 更 在 其 上 層 上 以 大 於 Pw 讀 背 1 1 鈍 化 膜 1 0 之 開 □ 徑 照 相 抗 蝕 膜 1 2 被 圖 案 形 成 〇 之 注 1 I 意 1 I 在 此 照 相 抗 蝕 膜 1 2 係 接 著 以 被 成 膜 之 Β L Μ 膜 事 項 1 I 再 1 I 之 膜 厚 ( 1 2 β m ) 之 2 倍 以 上 ( 3 β m ) 之 膜 厚 實 施 填 % 1 本 Γ^Ι 圖 案 形 成 〇 又 將 該 基 板 搬 送 至 在 高 真 空 下 與 金 屬 成 膜 裝 頁 'w*· 1 I 置 連 結 之 如 第 2 圖 所 示 之 平 行 平 板 型 R F 電 漿 處 理 裝 置 內 1 I > 作 爲 — 例 以 下 述 條 件 來 進 行 金 屬 成 膜 前 處 理 〇 1 1 1 氫 氣 流 量 3 0 S C C m 1 訂 氣 氣 壓 力 5 m T 0 r r ( 0 6 7 P a ) 1 1 高 周 波 電 力 二 3 0 0 W ( 1 3 5 6 Μ Η Z ) 1 1 處 理 時 間 6 分 鐘 1 1 該 電 漿 處 理 結 果 被 處 理 基 板 3 之 狀 態 係 如 第 1 ( b 边 I ) 圖 所 示 照 相 抗 蝕 膜 1 2 之 表 面 層 接 受 A r +離子照射 1 I » 因 熱 膨 脹 其 上 部 向 、f- 刖 突 出 抗 蝕 圖 案 之 斷 面 變 形 成 如 突 1 1 1 出 部 1 2 a 之 外 伸 狀 〇 1 1 I 再 者 以 該 條 件 作 處 理 時 基 板 表 面 之 最 高 溫 度 約 1 爲 1 1 5 °c 1 3 5 °c 〇 1 其 次 將 已 實 施 成 膜 前 處 理 之 該 被 處 理 基 板 3 介 由 1 1 閘 閥 在 高 真 空 下 搬 送 至 被 連 接 之 噴 鍍 裝 置 等 之 金 屬 成 1 | 膜 裝 置 1 例 如 將 路 膜 0 • 1 β m 銅 膜 1 0 β m 金 膜 1 1 本紙張尺度適用中囷國家標準(CNS ) A4規格(2I0x 297公釐) -9 - 經濟部中央標準局貝工消費合作社印袈 A7 ___B7_ 五、發明説明(7 ) 0 · l#m依序噴鑛積層,來形成BLM膜13。以第1 (c)圖來表示該狀態。 憑藉前述之金靥膜成膜前處理’外伸形狀被控制’在 基底抗蝕圖案之側壁面上,不致形成金屬膜’ B LM膜1 3係在電極襯墊9上之開口部和抗蝕膜12間被分開隔斷 〇 又,將該狀態之被處理基板7作爲一例’浸於由 D i m e t h y 1 S u 1 f ο X i d e ( C Η 3 ) 2 S 0 及 N - m e t h y 1 - 2-
Pyrrolidone CH3NC4He〇所構成之抗蝕剝離液內,處理( 在約9 5 °C之加熱溶液作中搖動處理)結果,如第1 (d )圖所示,形成於照相抗蝕膜1 2上之不要的B LM膜, 係在抗蝕膜剝離時同時被剝離,如第1 ( d )圖所示,完 成連接孔1 1之所規定之處之BLM膜圖案1 3 a。 實施例2 本實施例係同樣將本發明應用於錫焊球突出形成時之 B L Μ膜之圖案形成,在金屬膜噴鍍過程之成膜前處理, 使用以 I C P ( Inductively Coupled Plasma)爲電獎產 生源之電漿處理裝置,來實施本發明者。在本實施例中所 使用之被處理基板,係與實施例1所使用之基板相同(如 第1 (a)圖所示),故省略重複說明。 照相抗蝕膜1 2係與實施例1之情況相同,係以接著 被成膜之BLM膜13之膜厚(1.2Mm)之2倍以上 (3 #m)之膜厚實施圖案形成。 本紙張尺度適用中國國家標準(CNS ) A4規格(210X297公釐) ~' -10 - (請先閲讀背面之注意事項再填寫本頁)
經濟部中央橾準局貝工消費合作社印製 A7 _B7 _五、發明説明(8 ) 茲參照第3圖、第4圖來說明在本實施例之金屬成膜 前處理中,所使用之I C P處理裝置之概略構成例。本裝 置係由石英等電介材料所構成之電漿處理室2,以多層繞 於側壁之感應耦合線圈1 4,將電漿電源1 5之動力供給 電漿處理室2,在此形成高密度的電漿1 6 »被處理基板. 3係被載置於被供給基板偏壓電源17之基板階台4上, 實施所希望之電漿處理。再者,雖然在圖中被省略,此裝 置具備所必須具備之處理氣體導入孔、真空排氣系統、閘 閥和被處理基板之輸送系統。本裝置之特徵爲,憑藉大型 多繞感應耦合線圈1 4,使大電力之電漿激勵成爲可能, 而可實施1 0 12/ c m3程度之高密度電漿之處理。 又,憑藉基板偏壓電源1 7,可以使離子之入射能與 電漿生成獨立地控制。 又,在本實施例中,爲了提高被處理基板3之溫度控 制特性,基板階台4係如第4圖所示,利用在階台4內部 循環之冷媒來調整溫度,階台表面係憑藉靜電夾頭1 8之 靜電吸著及氣體冷卻來進行與被處理基板3間之良好的熱 傳遞。 因此,即使進行連績處理,亦可更精密控制金屬膜成 膜前處理中之基板溫度。 作爲與本實施例使用之I C P同等之裝置,可使用T C P ( Transfer Coupled Plasma ) * E C R ( Electron Coup 1 ed Resonance ),螺旋波(he 1 i con wave)電獎 等,若使用這些裝置,即可得到1 x 1 O^cm-3至1 x 本^張尺度適用t國國家標準(CNS ) A4規格(210X297公釐) (請先閲讀背面之注意事項再填寫本頁) -11 - 312812 A7 B7 五、發明説明(9 ) 1 0 14c m_3之電漿密度。 其次*將如第1 ( a )圖所示之被處理基板7設置於 階台4,作爲一例,以下述條件來實施金屬膜成膜前處理 經濟部中央樣準局貝工消費合作社印製 Μ氣體流量:25 seem 氣體壓力:lmTorr 電漿電源電力:1 000W(2MH 基板偏壓電壓:200V (13. 5 處理時間:4 5秒 在前述實施例1之平行平板型電漿處 爲了安定地持續放電,且確保處理速度之 加一定程度以上之RF電力,惟此時亦必 壓(陰極下降電壓)設定爲高零壓。 針對此問題,本實施例因爲使用可獨 電壓及電漿生成之2個具有高周波電源之 所以不致影響放電電漿,而因爲可使入射 ,所以不會有將過多熱變質給予抗蝕膜內 至基底上之事,可精密地設定基板偏壓電 對於剝離,加工至最適當形狀。 又,因爲使用高密度電漿源,所以可 之絕對量,且可在低壓力下設定條件,因 子之散亂,所以即使減低基板偏壓電壓亦 6 Μ Η z ) 理裝置之場合, 均一性,需要施 然將基板偏壓電 立控制基 電漿處理 離子能爲 部,而發 壓而將抗 以增大生 爲能抑制 可縮短處 板偏壓 裝置, 最佳化 生燒著 蝕膜, 成離子 入射離 理時間 因此,在本實施例中,可以比實施例1更加地大幅縮 本紙張尺度適用中國國家標準(CNS ) Α4規格(210Χ297公釐) (請先閲讀背面之注意事項再填寫本頁) 訂 功‘ ! -1 9 - 12 經濟部中央揉準局貝工消费合作社印製 A7 ___B7 _五、發明説明(1()) 短處理時間。此電漿處理結果,與實施例1同樣地,被處 理基板7係如第1(b)圖所示,照相抗蝕膜12之表面 層接受A r +離子照射,由於熱膨脹致其上部往外突出, 抗蝕圖案之斷面係變形成爲外伸狀。 再者,以本實施例之條件處理時,晶圓表面之最高到 達溫度亦約爲115 °C〜135 °C。 然後,經金屬膜形成,剝離後,與實施例1同樣地, 最後可實現金屬膜(B LM膜)之良好之圖案之形成。 以上,根據2種實施例來說明本發明,惟本發明並不 只限定在這些實施例,只要在不脫離本發明之主旨的範圍_ 內,可適宜地選擇樣品構造、處理裝置、處理條件等。 〔發明之效果〕 憑藉採用本發明,使用照相抗蝕膜之剝離處理法,在 將金屬膜圖案形成時之金屜膜成膜前處理中,不致使抗蝕 膜受到過多之熱變質而引起燒著至基底,可將抗蝕膜加工 成最適合剝離之狀態,可實現錫焊球突出形成用之B LM 膜之良好之圖案形成》 因此,若憑藉本發明,根據更微細化之設計規則,對. 於要求高集積度,高性能,高信賴性之半導體裝置之製造 極爲有效。 〔圖示之簡單說明〕 第1圖係按照過程順序表示適用本發明之被處理基板 本紙張尺度適用中國國家標準(CNS ) A4規格(2IOX 297公釐) (請先閲讀背面之注意事項再填寫本頁}
-13 - A7 B7 經濟部中央標準局員工消费合作社印製 五、發明説明(11 ) 狀態之斷面圖。 (a )在面對電極襯墊之鈍化膜連接孔周邊上,照相 抗蝕膜被形成之狀態。 (b )憑藉成膜前處理,使照相抗蝕膜開口端之形狀 變化之狀態。 (c)BLM膜之成膜狀態。 (d )憑藉剝離來完成B LM膜之圖案形成之狀態。 第2圖係平行平板型電漿處理裝置之概略斷面圖。 第 3 圖係裝載 I C P ( Inductively Coupled· Plasma )之電漿處理裝置之概略斷面圖9 第4圖係具備溫度控制機構之基板階台之概略斷面圖 〇 第5圖係將被處理基板狀態依過程順序來表示之使用 以往之薄膜抗蝕圖案時之斷面圖。 (a )在面對電極襯墊之鈍化膜連接孔周邊,照相抗 蝕膜被形成之狀態。 (b )憑藉成膜前處理,照相抗蝕膜之開口狀態僅稍' 變化之狀態。 (c)BLM膜成膜之狀態。 (d )無法進行抗蝕膜之剝離,而無法憑藉剝離來完 成圖案之狀態。 第6圖係在以往之晶圓溫度上昇速度很大之條件下, 將形成金屬膜之被處理基板之狀態,依過程順序表示之斷 面圖。 (請先閲讀背面之注意事項再填寫本頁) 訂 本紙張尺度適用中國國家標準(CNS ) A4規格(210 X 297公釐) 14 A7 B7 經濟部中央樣準局貝工消費合作社印裝 五、發明説明(12 ) (a )在面對電極襯墊之鈍化膜之連接孔周邊,厚膜 之照相抗蝕膜被形成之狀態。 (b )憑藉成膜前處理,使照相抗蝕膜之開口端形狀 變化之狀態。 (c)BLM膜成膜之狀態。 (d )無法進行抗蝕膜之剝離,無法憑藉剝離來完成 圖案之狀態。 〔圖號說明〕 1 :平行平板型電漿處理裝置 2 :電漿處理室 3 :被處理基板(晶圓) 4 :基板階台 5 :陽極板 6 :高周波電源 7 :耦合用電容器 8 :半導體基板 9 :電極襯墊 1 0 :鈍化膜 1 1 :連接孔 1 2 :照相抗蝕膜 1 2 a :突出部 13 :金屬膜(BLM膜) 13a :金屬膜(BLM膜)圖案 (請先閲讀背面之注意事項再填寫本頁) 訂 本紙張尺度適用t國國家標準(CNS ) A4規格(210X297公釐) -15 - A7 B7 五、發明説明(13) 1 4 :感應耦合線圈 1 5 :電漿電源
源 電 壓盤 偏夾 獎板電 電基靜 6 7 8 τχ II- IX (請先閱讀背面之注意事項再填寫本頁)
、tT 經濟部中央標準局員工消費合作社印製 本紙張尺度適用中國國家標準(CNS ) A4規格(210X 297公釐) 16 -
Claims (1)
- 經濟部中央榡準局員工消費合作社印製 A8 B8 C8 D8六、申請專利範圍 1. 一種金靥膜之圖案形成法,係針對於依序將電極 襯墊、表面保護膜、照相抗蝕膜層叠稹於半導體基板上之 被處理基板, 實施電漿照射處理, 叠積金屬膜層, 實施剝離處理之金靥膜之圖案形成法中,其特徵爲: 將前述照相抗蝕膜之厚度形成爲前述金屬膜之厚度 之2倍以上。 2. 如申請專利範圍第1項所述之金屬膜之圖案形成 法, 係將前述被處理基板之表面最高到達溫度設定爲 1 0 0 °C〜1 5 0 °C之處理條件。 3. 如申請專利範圍第1項所述之金靥膜之圖案之形 成法,係使用具有可得到I C P ( Inductively Coupled Plasma) · T C P ( Transfer Coupled Plasma) E C R ( Electron Coupled Resonance),螺旋波( helicon wave)電漿等,電漿密度在1 x 1 One m_3至 1 x 1 0 1 4 c m_3之間之高密度電漿源之電將處理裝置 (請先閱讀背面之注意事項再填寫本頁) 裝· 訂 本紙張尺度適用中國國家標準(CNS > A4規格(210X297公釐> 17 -
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TW085104857A TW312812B (zh) | 1995-05-24 | 1996-04-23 |
Country Status (5)
Country | Link |
---|---|
US (1) | US5888892A (zh) |
JP (1) | JPH08321486A (zh) |
KR (1) | KR100345622B1 (zh) |
CA (1) | CA2177244C (zh) |
TW (1) | TW312812B (zh) |
Families Citing this family (19)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6410922B1 (en) | 1995-11-29 | 2002-06-25 | Konstantinos Evangelos Spartiotis | Forming contacts on semiconductor substrates for radiation detectors and imaging devices |
GB2352084B (en) * | 1999-07-13 | 2002-11-13 | Simage Oy | Forming contacts on semiconductor substrates for radiation detectors and imaging devices |
US20020158207A1 (en) * | 1996-11-26 | 2002-10-31 | Simage, Oy. | Forming contacts on semiconductor substrates for radiation detectors and imaging devices |
JP3587019B2 (ja) * | 1997-04-08 | 2004-11-10 | ソニー株式会社 | 半導体装置の製造方法 |
US6214717B1 (en) * | 1998-11-16 | 2001-04-10 | Taiwan Semiconductor Manufacturing Company | Method for adding plasma treatment on bond pad to prevent bond pad staining problems |
US6440836B1 (en) * | 1999-03-16 | 2002-08-27 | Industrial Technology Research Institute | Method for forming solder bumps on flip chips and devices formed |
US6420252B1 (en) * | 2000-05-10 | 2002-07-16 | Emcore Corporation | Methods of forming robust metal contacts on compound semiconductors |
US6586323B1 (en) * | 2000-09-18 | 2003-07-01 | Taiwan Semiconductor Manufacturing Company | Method for dual-layer polyimide processing on bumping technology |
US6375062B1 (en) * | 2000-11-06 | 2002-04-23 | Delphi Technologies, Inc. | Surface bumping method and structure formed thereby |
US6372545B1 (en) | 2001-03-22 | 2002-04-16 | Taiwan Semiconductor Manufacturing Company | Method for under bump metal patterning of bumping process |
US6784089B2 (en) * | 2003-01-13 | 2004-08-31 | Aptos Corporation | Flat-top bumping structure and preparation method |
KR100510543B1 (ko) * | 2003-08-21 | 2005-08-26 | 삼성전자주식회사 | 표면 결함이 제거된 범프 형성 방법 |
KR101112538B1 (ko) * | 2004-07-27 | 2012-03-13 | 삼성전자주식회사 | 박막 트랜지스터 표시판 및 그 제조 방법 |
US9929080B2 (en) * | 2004-11-15 | 2018-03-27 | Intel Corporation | Forming a stress compensation layer and structures formed thereby |
US7713860B2 (en) * | 2007-10-13 | 2010-05-11 | Wan-Ling Yu | Method of forming metallic bump on I/O pad |
JP2010205829A (ja) * | 2009-03-02 | 2010-09-16 | Mitsubishi Electric Corp | 半導体発光素子及びその製造方法 |
CN111554581A (zh) * | 2020-04-07 | 2020-08-18 | 厦门通富微电子有限公司 | 一种导电柱的形成工艺及封装体 |
CN111668184B (zh) * | 2020-07-14 | 2022-02-01 | 甬矽电子(宁波)股份有限公司 | 引线框制作方法和引线框结构 |
CN117791297A (zh) * | 2023-12-26 | 2024-03-29 | 武汉敏芯半导体股份有限公司 | 半导体激光器的电极的制备方法及电极 |
Family Cites Families (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4933303A (en) * | 1989-07-25 | 1990-06-12 | Standard Microsystems Corporation | Method of making self-aligned tungsten interconnection in an integrated circuit |
DE69014871T2 (de) * | 1990-07-31 | 1995-05-24 | Ibm | Verfahren zur Bildung metallischer Kontaktflächen und Anschlüsse auf Halbleiterchips. |
JP3294411B2 (ja) * | 1993-12-28 | 2002-06-24 | 富士通株式会社 | 半導体装置の製造方法 |
US5393697A (en) * | 1994-05-06 | 1995-02-28 | Industrial Technology Research Institute | Composite bump structure and methods of fabrication |
US5486483A (en) * | 1994-09-27 | 1996-01-23 | Trw Inc. | Method of forming closely spaced metal electrodes in a semiconductor device |
-
1995
- 1995-05-24 JP JP7125119A patent/JPH08321486A/ja active Pending
-
1996
- 1996-04-23 TW TW085104857A patent/TW312812B/zh not_active IP Right Cessation
- 1996-05-22 US US08/650,271 patent/US5888892A/en not_active Expired - Lifetime
- 1996-05-22 KR KR1019960017378A patent/KR100345622B1/ko not_active IP Right Cessation
- 1996-05-23 CA CA002177244A patent/CA2177244C/en not_active Expired - Fee Related
Also Published As
Publication number | Publication date |
---|---|
CA2177244A1 (en) | 1996-11-25 |
KR960042972A (ko) | 1996-12-21 |
CA2177244C (en) | 2007-10-09 |
KR100345622B1 (ko) | 2002-11-30 |
JPH08321486A (ja) | 1996-12-03 |
US5888892A (en) | 1999-03-30 |
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