JPH03203323A - 半導体装置の製造方法 - Google Patents

半導体装置の製造方法

Info

Publication number
JPH03203323A
JPH03203323A JP2050785A JP5078590A JPH03203323A JP H03203323 A JPH03203323 A JP H03203323A JP 2050785 A JP2050785 A JP 2050785A JP 5078590 A JP5078590 A JP 5078590A JP H03203323 A JPH03203323 A JP H03203323A
Authority
JP
Japan
Prior art keywords
insulating film
opening
conductor
forming
film
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP2050785A
Other languages
English (en)
Japanese (ja)
Inventor
Kyungseok Oh
オ・キョンソク
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Samsung Electronics Co Ltd
Original Assignee
Samsung Electronics Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Samsung Electronics Co Ltd filed Critical Samsung Electronics Co Ltd
Publication of JPH03203323A publication Critical patent/JPH03203323A/ja
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76897Formation of self-aligned vias or contact plugs, i.e. involving a lithographically uncritical step
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76829Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers
    • H01L21/76831Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers in via holes or trenches, e.g. non-conductive sidewall liners
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/48Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/482Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of lead-in layers inseparably applied to the semiconductor body
    • H01L23/485Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of lead-in layers inseparably applied to the semiconductor body consisting of layered constructions comprising conductive layers and insulating layers, e.g. planar contacts
    • H01L23/4855Overhang structure
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001Technical content checked by a classifier
    • H01L2924/0002Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Semiconductor Memories (AREA)
  • Electrodes Of Semiconductors (AREA)
JP2050785A 1989-12-29 1990-02-28 半導体装置の製造方法 Pending JPH03203323A (ja)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
KR89-20099 1989-12-29
KR1019890020099A KR910013463A (ko) 1989-12-29 1989-12-29 반도체 소자의 개구형성방법

Publications (1)

Publication Number Publication Date
JPH03203323A true JPH03203323A (ja) 1991-09-05

Family

ID=19294139

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2050785A Pending JPH03203323A (ja) 1989-12-29 1990-02-28 半導体装置の製造方法

Country Status (4)

Country Link
JP (1) JPH03203323A (de)
KR (1) KR910013463A (de)
DE (1) DE4018437A1 (de)
GB (1) GB2239559A (de)

Families Citing this family (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR920015542A (ko) * 1991-01-14 1992-08-27 김광호 반도체장치의 다층배선형성법
KR950011556B1 (ko) * 1992-07-03 1995-10-06 현대전자산업주식회사 반도체 접속장치 형성방법
DE4309611A1 (de) * 1993-03-24 1994-09-29 Siemens Ag Herstellverfahren für ein Kontaktloch
DE4442652A1 (de) * 1994-11-30 1996-01-25 Siemens Ag Verfahren zur Herstellung eines Kontaktloches auf eine Metallisierungsebene einer dreidimensionalen Schaltungsanordnung

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6010754A (ja) * 1983-06-30 1985-01-19 Toshiba Corp 半導体装置及びその製造方法
JPS6278853A (ja) * 1985-09-30 1987-04-11 Nec Corp 半導体装置の製造方法
JPS6386455A (ja) * 1986-09-29 1988-04-16 Mitsubishi Electric Corp 半導体装置
JPS6484735A (en) * 1987-09-28 1989-03-30 Toshiba Corp Manufacture of semiconductor device

Family Cites Families (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4641420A (en) * 1984-08-30 1987-02-10 At&T Bell Laboratories Metalization process for headless contact using deposited smoothing material
US4656732A (en) * 1984-09-26 1987-04-14 Texas Instruments Incorporated Integrated circuit fabrication process
GB2206729B (en) * 1987-07-01 1990-10-24 British Aerospace A method of forming electrical contacts in a multi-level interconnect system
JPH01289142A (ja) * 1988-05-16 1989-11-21 Nippon Telegr & Teleph Corp <Ntt> 垂直配線構造
GB2219434A (en) * 1988-06-06 1989-12-06 Philips Nv A method of forming a contact in a semiconductor device

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6010754A (ja) * 1983-06-30 1985-01-19 Toshiba Corp 半導体装置及びその製造方法
JPS6278853A (ja) * 1985-09-30 1987-04-11 Nec Corp 半導体装置の製造方法
JPS6386455A (ja) * 1986-09-29 1988-04-16 Mitsubishi Electric Corp 半導体装置
JPS6484735A (en) * 1987-09-28 1989-03-30 Toshiba Corp Manufacture of semiconductor device

Also Published As

Publication number Publication date
DE4018437A1 (de) 1991-07-11
GB2239559A (en) 1991-07-03
KR910013463A (ko) 1991-08-08
GB9013153D0 (en) 1990-08-01

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