JPH0313757B2 - - Google Patents
Info
- Publication number
- JPH0313757B2 JPH0313757B2 JP56052663A JP5266381A JPH0313757B2 JP H0313757 B2 JPH0313757 B2 JP H0313757B2 JP 56052663 A JP56052663 A JP 56052663A JP 5266381 A JP5266381 A JP 5266381A JP H0313757 B2 JPH0313757 B2 JP H0313757B2
- Authority
- JP
- Japan
- Prior art keywords
- base region
- region
- buried layer
- conductivity type
- epitaxial layer
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
Classifications
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
- G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
- G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
- G11C11/41—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming static cells with positive feedback, i.e. cells not needing refreshing or charge regeneration, e.g. bistable multivibrator or Schmitt trigger
- G11C11/411—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming static cells with positive feedback, i.e. cells not needing refreshing or charge regeneration, e.g. bistable multivibrator or Schmitt trigger using bipolar transistors only
- G11C11/4116—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming static cells with positive feedback, i.e. cells not needing refreshing or charge regeneration, e.g. bistable multivibrator or Schmitt trigger using bipolar transistors only with at least one cell access via separately connected emittors of said transistors or via multiple emittors, e.g. T2L, ECL
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B10/00—Static random access memory [SRAM] devices
- H10B10/10—SRAM devices comprising bipolar components
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
- H10D62/10—Shapes, relative sizes or dispositions of the regions of the semiconductor bodies; Shapes of the semiconductor bodies
- H10D62/17—Semiconductor regions connected to electrodes not carrying current to be rectified, amplified or switched, e.g. channel regions
- H10D62/177—Base regions of bipolar transistors, e.g. BJTs or IGBTs
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
- H10D84/60—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups H10D10/00 or H10D18/00, e.g. integration of BJTs
- H10D84/611—Combinations of BJTs and one or more of diodes, resistors or capacitors
- H10D84/613—Combinations of vertical BJTs and one or more of diodes, resistors or capacitors
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- H10W42/25—
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Computer Hardware Design (AREA)
- Semiconductor Memories (AREA)
- Bipolar Transistors (AREA)
Priority Applications (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP56052663A JPS57167675A (en) | 1981-04-08 | 1981-04-08 | Semiconductor device |
| US06/366,278 US4550390A (en) | 1981-04-08 | 1982-04-07 | Semiconductor memory device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP56052663A JPS57167675A (en) | 1981-04-08 | 1981-04-08 | Semiconductor device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS57167675A JPS57167675A (en) | 1982-10-15 |
| JPH0313757B2 true JPH0313757B2 (enExample) | 1991-02-25 |
Family
ID=12921100
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP56052663A Granted JPS57167675A (en) | 1981-04-08 | 1981-04-08 | Semiconductor device |
Country Status (2)
| Country | Link |
|---|---|
| US (1) | US4550390A (enExample) |
| JP (1) | JPS57167675A (enExample) |
Families Citing this family (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS60143496A (ja) * | 1983-12-29 | 1985-07-29 | Fujitsu Ltd | 半導体記憶装置 |
| US4669180A (en) * | 1984-12-18 | 1987-06-02 | Advanced Micro Devices, Inc. | Method of forming emitter coupled logic bipolar memory cell using polysilicon Schottky diodes for coupling |
| JPS61234068A (ja) * | 1985-04-10 | 1986-10-18 | Nec Corp | バイポ−ラram |
| JPH0746702B2 (ja) * | 1986-08-01 | 1995-05-17 | 株式会社日立製作所 | 半導体記憶装置 |
| US4852060A (en) * | 1988-03-31 | 1989-07-25 | International Business Machines Corporation | Soft error resistant data storage cells |
| US6005801A (en) * | 1997-08-20 | 1999-12-21 | Micron Technology, Inc. | Reduced leakage DRAM storage unit |
| US9461035B2 (en) | 2012-12-28 | 2016-10-04 | Texas Instruments Incorporated | High performance isolated vertical bipolar junction transistor and method for forming in a CMOS integrated circuit |
Family Cites Families (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US3909807A (en) * | 1974-09-03 | 1975-09-30 | Bell Telephone Labor Inc | Integrated circuit memory cell |
| US4366554A (en) * | 1978-10-03 | 1982-12-28 | Tokyo Shibaura Denki Kabushiki Kaisha | I2 L Memory device |
| JPS55158659A (en) * | 1979-05-30 | 1980-12-10 | Chiyou Lsi Gijutsu Kenkyu Kumiai | Semiconductor memory storage |
| JPS564263A (en) * | 1979-06-25 | 1981-01-17 | Hitachi Ltd | Semiconductor memory |
| JPS5842556B2 (ja) * | 1979-08-30 | 1983-09-20 | 富士通株式会社 | 半導体記憶装置 |
| JPS5829628B2 (ja) * | 1979-11-22 | 1983-06-23 | 富士通株式会社 | 半導体記憶装置 |
-
1981
- 1981-04-08 JP JP56052663A patent/JPS57167675A/ja active Granted
-
1982
- 1982-04-07 US US06/366,278 patent/US4550390A/en not_active Expired - Lifetime
Also Published As
| Publication number | Publication date |
|---|---|
| JPS57167675A (en) | 1982-10-15 |
| US4550390A (en) | 1985-10-29 |
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