JPH0259493B2 - - Google Patents

Info

Publication number
JPH0259493B2
JPH0259493B2 JP58191616A JP19161683A JPH0259493B2 JP H0259493 B2 JPH0259493 B2 JP H0259493B2 JP 58191616 A JP58191616 A JP 58191616A JP 19161683 A JP19161683 A JP 19161683A JP H0259493 B2 JPH0259493 B2 JP H0259493B2
Authority
JP
Japan
Prior art keywords
block
buffer storage
tag
sub
data
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
JP58191616A
Other languages
English (en)
Japanese (ja)
Other versions
JPS6083156A (ja
Inventor
Masahiro Kuryama
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP58191616A priority Critical patent/JPS6083156A/ja
Publication of JPS6083156A publication Critical patent/JPS6083156A/ja
Publication of JPH0259493B2 publication Critical patent/JPH0259493B2/ja
Granted legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
    • G06F12/0844—Multiple simultaneous or quasi-simultaneous cache accessing

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Memory System Of A Hierarchy Structure (AREA)
JP58191616A 1983-10-13 1983-10-13 バツフアストレ−ジ制御方式 Granted JPS6083156A (ja)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP58191616A JPS6083156A (ja) 1983-10-13 1983-10-13 バツフアストレ−ジ制御方式

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP58191616A JPS6083156A (ja) 1983-10-13 1983-10-13 バツフアストレ−ジ制御方式

Publications (2)

Publication Number Publication Date
JPS6083156A JPS6083156A (ja) 1985-05-11
JPH0259493B2 true JPH0259493B2 (enExample) 1990-12-12

Family

ID=16277594

Family Applications (1)

Application Number Title Priority Date Filing Date
JP58191616A Granted JPS6083156A (ja) 1983-10-13 1983-10-13 バツフアストレ−ジ制御方式

Country Status (1)

Country Link
JP (1) JPS6083156A (enExample)

Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS62118456A (ja) * 1985-11-19 1987-05-29 Nec Corp キヤツシユメモリ
JPH0290348A (ja) * 1988-09-28 1990-03-29 Nec Corp データ無効化サイズ可変なキャッシュメモリシステム
JP5293001B2 (ja) * 2008-08-27 2013-09-18 日本電気株式会社 キャッシュメモリ装置及びその制御方法

Family Cites Families (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS57167188A (en) * 1981-04-06 1982-10-14 Nippon Telegr & Teleph Corp <Ntt> Buffer memory controlling system

Also Published As

Publication number Publication date
JPS6083156A (ja) 1985-05-11

Similar Documents

Publication Publication Date Title
EP0095033B1 (en) Set associative sector cache
US4115855A (en) Buffer memory control device having priority control units for priority processing set blocks and unit blocks in a buffer memory
JPH0877066A (ja) フラッシュメモリコントローラ
US4494157A (en) Information readout apparatus
EP0093428B1 (en) Buffer storage including a swapping circuit
JPH0259493B2 (enExample)
JPH11191900A (ja) オーディオデータ処理装置
JPS60120450A (ja) バッファメモリ制御方式
JPH0551933B2 (enExample)
JPH0795307B2 (ja) キャッシュメモリ制御回路
KR100385238B1 (ko) 그룹적응형세그먼트캐시버퍼구현방법
JPS59218692A (ja) ロジカルバツフア記憶制御方式
JPS6022777B2 (ja) デ−タ転送方式
JPS59167891A (ja) 緩衝記憶装置
JP2963257B2 (ja) 処理装置
JPH0250743A (ja) 外部記憶サブシステム
JPH0883213A (ja) キャッシュメモリを含む記憶装置
JPH024020B2 (enExample)
JPS59146344A (ja) 仮想スタツク先行制御方式
JPS59178671A (ja) バツフアストレイジリプレイス方式
JPS60237563A (ja) バス結合装置の高速転送方法
JPS6037932B2 (ja) キャッシュメモリ制御方式
JPS609296B2 (ja) バッファメモリ制御方式
JPS623360A (ja) 情報処理装置
JPS63143647A (ja) 多重階層記憶方式