JPH0259493B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION (a) Technical Field of the Invention The present invention relates to a buffer storage control method in a data processing system having buffer storage between a main storage device and a central processing unit.

(b) Background of the technology As data processing systems have become larger and faster in recent years, it has become necessary to speed up the access time to the main memory. Buffer storage, which is faster than main memory but has a smaller storage capacity, is installed in the system, and when the central processing unit accesses main memory, the buffer storage is first accessed and the necessary data is stored there. If not, by transferring the data from the main memory to the buffer storage and then controlling the access to the buffer storage, it is possible to control the apparent access to the main memory from the central processing unit's perspective. There are known methods to shorten the time.

In such a data processing system, in order to improve processing capacity, it is essential to improve the hit rate for buffer storage.

Therefore, there has been a need for a method to improve the hit rate without increasing the capacity of the tag section of the buffer storage, which would cause an increase in costs, and without increasing the transfer time.

(c) Conventional technology and problems Conventionally, in buffer storage,
The main storage and buffer storage were divided into blocks of the same size and constant capacity, and data transfer between the main storage and buffer storage and allocation of buffer storage areas were performed in units of blocks. .

Furthermore, in buffer storage, improving the hit rate and shortening the data move-in time are the biggest factors in improving the performance of the data processing system.

One way to achieve the above objective is to increase the capacity of buffer storage. The data move-in unit (ie, block) is reduced. There is a way.

However, increasing the capacity of the buffer storage generally means increasing the capacity of the tag section, but the tag section often uses particularly expensive high-speed memory, resulting in a significant increase in cost. There is also the risk of increasing cycle time due to increased capacity.

Therefore, if you try to increase the buffer storage capacity without increasing the tag capacity,
The capacity of the block increases, and the move-in time increases. If we simply tried to make the block smaller, we would have the problem of increasing the number of tags.

(d) Purpose of the Invention In view of the above-mentioned drawbacks of the conventional art, the present invention provides a method for moving in buffer storage from the main storage device to buffer storage without changing the unit of move-in size and without changing the capacity of the tag section. The objective is to provide a method to improve the rate.

(e) Structure of the Invention The object of the present invention is to provide a data processing system having a buffer storage between a main memory and a central processing unit, in which one block of the data section of the buffer storage is used as a sub-block, and a plurality of One entry in the tag part is provided for each sub-block, and a valid bit is provided in one entry in the tag part corresponding to each sub-block included in the tag part, and data read from the buffer storage and move-in from the main memory to the buffer storage are performed. This was achieved using a buffer storage control method characterized by control in sub-block units, which shortened the move-in time without increasing the capacity of the tag section of the buffer storage. It has the advantage of increasing capacity and improving the hit rate for buffer storage.

(f) Examples of the invention Examples of the invention will be described in detail below with reference to the drawings.
Figure 1 is a diagram explaining the concept of the present invention, and Figure 2 is a diagram explaining the concept of the present invention.
FIG. 1 is a block diagram showing an embodiment of the present invention.

In FIG. 1, the relationship between the main storage device (hereinafter referred to as MS) and the buffer storage (hereinafter referred to as BS) is explained in the case where A is a conventional example and B is a case where the present invention is implemented.

In this figure, B0 to B9 indicate the aforementioned blocks, and A0 to A3 and A0' to A6' indicate addresses in block units for each block, respectively.

In the present invention, as is clear from (b), BS
In order to improve the performance of the BS, one conventional block in the data section of the BS is made into one subblock, and multiple (in this example, two) subblocks are replaced with one in the conventional example.
It is compatible with blocks. Corresponding examples of the size of one block between the conventional example and the present invention are shown in thick line frames.

The tag section has one entry corresponding to one block of the data section, and this entry is expanded by several bits to provide valid bits corresponding to each sub-block to indicate the validity of each sub-block. . In this example, V0 and V1 are provided corresponding to two sub-blocks, and V0
is a valid bit corresponding to sub-block 0, and V1 is a valid bit corresponding to sub-block 1.

Therefore, the number of address bits in the tag part can be reduced by the amount that increases the capacity of one block (in this example, twice the capacity), so even if the number of valid bits is increased by several bits, the overall The number of bits can be configured so as not to increase too much. (It has not increased in this example.) When implementing the present invention in a BS with the above configuration, move-in is performed in sub-block units, but when moving in the first sub-block within the block, even if it is sub-block 0. For example, the address of the block and the valid bit V0 corresponding to the sub-block are registered in the entry in the tag section, but only the valid bit V1 is turned on for move-ins of subsequent sub-blocks within the same block. to control.

When accessing a BS, only the block address and valid bits of the corresponding subblock are checked. That is, if the valid bit of the corresponding sub-block of the entry in the tag part with the matching block address is on, it will be hit regardless of the values of other valid bits, but if there is no entry in the tag part with the matching block address, or
Even if a subblock exists, if the valid bit of the corresponding subblock is off, it is treated as a non-hit.

Replacement when a new block becomes necessary using all accessible blocks registered in the BS is controlled on a tag entry basis (that is, on a block-by-block basis).

By controlling in this way, it is possible to shorten the move-in time and increase the BS capacity (in this example, double the capacity) and improve the hit rate without increasing the capacity of the tag part. .

Next, an embodiment of the present invention will be described with reference to FIG.

In this figure, 1 is the BS address register (BSAR), 2 is the BS tag section (TAG), 3 is the BS data section (DATA), and 4 is the comparator (C). The upper bit and the registered address (A) of the tag section (TAG) 2 are compared, and if they match, a match signal (M) is output. 51, 52,
61 and 62 are logic circuits, 53 is an OR circuit, 6
3, 64, and 65 are negative circuits. Then, V0, V indicated in the tag part (TAG) 2
1 is a valid bit for the sub-blocks constituting each block as explained in FIG.
is the registered address.

Furthermore, in this embodiment, as explained with reference to FIG. 1, one block is composed of two sub-blocks, so the address bit for identifying one of them is indicated by S.

Now, a memory address is set in the BS address register (BSAR) 1 from the central processing unit (not shown), and when the BS is accessed, the upper bits of the BS address register (BSAR) 1 and the tag part (TAG) 2 are set. The registered address is compared with the registered address in the comparator (C) 4, and if a match signal (M) is obtained and the corresponding valid bits V0 and V1 are on, the above S bit of the BS address register (BSAR) 1 is set. As a result, an AND is performed in either of the AND circuits 51 and 52, and it is indicated through the OR circuit 53 that the data required by the central processing unit of the BS exists in one of the subblocks. Output signal HIT. In BS,
When the HIT signal is received, the data unit (DATA) 3 is controlled to output the data of the sub-block to the central processing unit.

In the present invention, the HIT signal is a sub-block (this one sub-block is one in the conventional BS).
Since the data is output in units (corresponding to blocks), it is possible to search a data section (DATA) 3 with twice the capacity using the tag section (TAG) 2, which has approximately the same capacity as the conventional one.

If the matching signal (M) is not obtained in the comparator (C) 4, or if the corresponding valid bit V
If 0, V1 is off, the data required by the central processing unit does not exist in the BS, so the data required by the central processing unit is stored from the main memory (not shown). needs to be moved to BS.

At this time, either the AND circuit 61 or 62 is selected by the S bit of the BS address register (BSAR) 1, and the valid bits V0, V1 are selected.
(i.e. disabling signal B1=0
), and if necessary, register the address in the address section A of the tag section (TAG) 2, and move the block data on the main memory corresponding to the address into the corresponding sub-block of the data section (DATA) 3. do.

As is clear from the above explanation, the present invention is characterized in that the tag part of the BS is provided in each block, but the search for the tag part and the move-in operation according to the search result are performed in sub-block units. There is.

(g) Effects of the Invention As explained in detail above, the buffer storage control method of the present invention provides buffer storage control in a data processing system having buffer storage between the main storage device and the central processing unit. One block of the data section of the tag is set as a subblock, and one tag entry is provided for multiple subblocks.
Valid bits are provided in one entry of the tag corresponding to the sub-blocks, and memory access to the buffer storage and move-in from the main storage to the buffer storage are controlled in units of the above-mentioned sub-blocks. While the move-in time is shortened without substantially increasing the capacity of the tag section of the storage, the capacity of the buffer storage is increased and the hit rate for the buffer storage is improved.

[Brief explanation of drawings]

FIG. 1 is a diagram for explaining the concept of the present invention, and FIG. 2 is a block diagram showing an embodiment of the present invention. In the drawing, 1 is the BS address register (BSAR), 2 is the tag section (TAG), 3 is the data section (DATA), 4 is the comparator (C), V0 and V1 are valid bits for the subblocks that make up the block, and M is the valid bits for the subblocks that make up the block. The match signal and S represent address bits identifying sub-blocks within the block, respectively.

Claims (1)

[Claims] 1. In a data processing system having buffer storage between the main storage device and the central processing unit, one block of the data section of the buffer storage is defined as a subblock, one entry of the tag section is provided for multiple subblocks, and a tag section is provided for each subblock. A valid bit is provided in one entry of the section corresponding to each sub-block included therein, and data read from the buffer storage and move-in from the main memory to the buffer storage are controlled on a sub-block basis. Buffer storage control method.