JPS57167188A - Buffer memory controlling system - Google Patents

Buffer memory controlling system

Info

Publication number
JPS57167188A
JPS57167188A JP56052086A JP5208681A JPS57167188A JP S57167188 A JPS57167188 A JP S57167188A JP 56052086 A JP56052086 A JP 56052086A JP 5208681 A JP5208681 A JP 5208681A JP S57167188 A JPS57167188 A JP S57167188A
Authority
JP
Japan
Prior art keywords
subblock
subblocks
data
buffer memory
memory
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP56052086A
Other languages
Japanese (ja)
Inventor
Kazuo Tajiri
Akira Nakajima
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Nippon Telegraph and Telephone Corp
Original Assignee
Nippon Telegraph and Telephone Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Nippon Telegraph and Telephone Corp filed Critical Nippon Telegraph and Telephone Corp
Priority to JP56052086A priority Critical patent/JPS57167188A/en
Publication of JPS57167188A publication Critical patent/JPS57167188A/en
Pending legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
    • G06F12/0806—Multiuser, multiprocessor or multiprocessing cache systems

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Memory System Of A Hierarchy Structure (AREA)

Abstract

PURPOSE:To minimize the invalidating range when the data on a buffer memory is invalidated and to prevent the lowering of the hit factor, by adding the invalidity display bit to the tag array with every subblock on the buffer memory. CONSTITUTION:The blocks, i.e. the transfer unit between a main memory 7 and buffer memories 3, 4 are divided into subblocks. Then the bit showing the validity of the data is added to tag arrays 5 and 6 of buffer memories 3 and 4 with every subblock. For the coincident process of the data on the memories 3 and 4, only the validity display bit of some subblock is operated for invalidation, and the access is allowed to other subblocks. At the same time, if an access is given to the invalidated subblock, all invalid subblocks within a block including the relevant subblock are transferred from the memory 7.
JP56052086A 1981-04-06 1981-04-06 Buffer memory controlling system Pending JPS57167188A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP56052086A JPS57167188A (en) 1981-04-06 1981-04-06 Buffer memory controlling system

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP56052086A JPS57167188A (en) 1981-04-06 1981-04-06 Buffer memory controlling system

Publications (1)

Publication Number Publication Date
JPS57167188A true JPS57167188A (en) 1982-10-14

Family

ID=12905010

Family Applications (1)

Application Number Title Priority Date Filing Date
JP56052086A Pending JPS57167188A (en) 1981-04-06 1981-04-06 Buffer memory controlling system

Country Status (1)

Country Link
JP (1) JPS57167188A (en)

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6083156A (en) * 1983-10-13 1985-05-11 Fujitsu Ltd Buffer storage control system
JPS61228540A (en) * 1985-04-01 1986-10-11 Nec Corp Cache memory control system
JPS6339058A (en) * 1986-08-01 1988-02-19 Nec Corp Invalidating system for cache memory device
JPH03132858A (en) * 1989-10-19 1991-06-06 Agency Of Ind Science & Technol Buffer control system

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5489444A (en) * 1977-12-27 1979-07-16 Fujitsu Ltd Associative memory processing system

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5489444A (en) * 1977-12-27 1979-07-16 Fujitsu Ltd Associative memory processing system

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6083156A (en) * 1983-10-13 1985-05-11 Fujitsu Ltd Buffer storage control system
JPH0259493B2 (en) * 1983-10-13 1990-12-12 Fujitsu Ltd
JPS61228540A (en) * 1985-04-01 1986-10-11 Nec Corp Cache memory control system
JPS6339058A (en) * 1986-08-01 1988-02-19 Nec Corp Invalidating system for cache memory device
JPH03132858A (en) * 1989-10-19 1991-06-06 Agency Of Ind Science & Technol Buffer control system

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