JPS5447531A - Memory control system for multi-processor system possessing intermediate buffer memory - Google Patents
Memory control system for multi-processor system possessing intermediate buffer memoryInfo
- Publication number
- JPS5447531A JPS5447531A JP11419677A JP11419677A JPS5447531A JP S5447531 A JPS5447531 A JP S5447531A JP 11419677 A JP11419677 A JP 11419677A JP 11419677 A JP11419677 A JP 11419677A JP S5447531 A JPS5447531 A JP S5447531A
- Authority
- JP
- Japan
- Prior art keywords
- memory
- memories
- intermediate buffer
- buffer memory
- buffer
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Abstract
PURPOSE:To secure a system constitution so as to avoid occurrence of conflict for the contents of the buffer memory, the intermediate buffer memory and the main memory respectively with no deterioration of the efficiency for the system as a whole. CONSTITUTION:The multi-processor system contains buffer memories 1-0, 1-2-1-n exclusive for plural units of CPU, main memory 4 which is shared by plural units of CPU, and intermediate buffer memory 2 which is located between buffer memories 1-0, 1-2-1-n and memory 4 and holds the copy the data of memory 4. Then intermediate buffer memory directory 3, possessing plural numbers of entry 6 corresponding to each block 5 in memory 3, is added, along with flag bits 7-0-7-n to show in much one of buffer memories 1-0-1-n the data within memories 1-0- 1-n is held. With use of bits 7-0-7-n, block 5 of memories 1-0-1-n holding the copy of block 5 is made invalid.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP11419677A JPS5447531A (en) | 1977-09-22 | 1977-09-22 | Memory control system for multi-processor system possessing intermediate buffer memory |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP11419677A JPS5447531A (en) | 1977-09-22 | 1977-09-22 | Memory control system for multi-processor system possessing intermediate buffer memory |
Publications (1)
Publication Number | Publication Date |
---|---|
JPS5447531A true JPS5447531A (en) | 1979-04-14 |
Family
ID=14631597
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP11419677A Pending JPS5447531A (en) | 1977-09-22 | 1977-09-22 | Memory control system for multi-processor system possessing intermediate buffer memory |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS5447531A (en) |
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH01314356A (en) * | 1988-06-14 | 1989-12-19 | Fujitsu Ltd | Key information processing system for multiprocessing system |
JP2008142105A (en) * | 2006-12-06 | 2008-06-26 | Yung-Fa Su | Buckle of belt |
-
1977
- 1977-09-22 JP JP11419677A patent/JPS5447531A/en active Pending
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH01314356A (en) * | 1988-06-14 | 1989-12-19 | Fujitsu Ltd | Key information processing system for multiprocessing system |
JP2008142105A (en) * | 2006-12-06 | 2008-06-26 | Yung-Fa Su | Buckle of belt |
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Legal Events
Date | Code | Title | Description |
---|---|---|---|
A762 | Written abandonment of application |
Free format text: JAPANESE INTERMEDIATE CODE: A762 Effective date: 20040830 |