JPH01314356A - Key information processing system for multiprocessing system - Google Patents

Abstract

PURPOSE:To improve the efficiency of processing by confirming a processor which reads out a key by a recording means when key information is rewritten and information only the processor of the rewriting of the key. CONSTITUTION:At the time of a 'key' read due to a TLB(Translation Lookaside Buffer) miss, a main controller 3 sets and records a flag corresponding to one of processors (1-1) to (1-n) which makes a read in a flag register provided additionally to a 'key' storage 4. Then when one processor rewrites the 'key' on the 'key' storage 4, the contents of the flag register corresponding to the 'key' are read out at the same time and only a processor which holds a copy of the 'key' in the TLB is informed that the copy of the 'key' is invalidated. Consequently, a processor for 'key' information with which whether or not a fast TLB search is made is determined is obtained.

Description

[Detailed Description of the Invention] [Summary] The present invention relates to a processing method when rewriting a "key" in a multiprocessing computer system having a plurality of processors.
The real address sent to the processor with the LB request is the TL
Since it is unknown whether the TLB entry is in the B entry or not, it is necessary to constantly read all TLB entries and check the addresses, which imposes an unnecessarily large processing burden on each processor. , Each “key” in the above “key” storage device is stored in the main controller.
Means for recording the readout operation of each processor for each information, and when the "key" information in the "key" storage device is rewritten, the processor that read out the "key" is confirmed by the recording means; , and means for notifying the PPTLB request only to the processor that has performed the reading.

[Industrial application field]

The present invention relates to a processing method for a "key" used for memory protection in a computer system, and particularly to a processing method for rewriting a "key" in a multiprocessing computer system having a plurality of processors. It is.

[Conventional technology]

In computer systems that use virtual addresses and obtain real addresses through address conversion, a method is usually used to obtain real addresses using segment tables and page tables. T L B (Translation
A side buffer) is used.

(TLB is made of elements with fast access time,
The virtual addresses of pages that are frequently accessed at that time are stored in a correspondence table with real addresses.

) In a multi-processing computer system including a plurality of processors, this TLB is provided for each processor and has a configuration as shown in FIG.

FIG. 5 shows a configuration diagram of a multiprocessing computer system having a plurality of processors, in which 51-1 to 51-n are processors, 52-
1 to 52-n are TLBs in the processor, 53 is a main controller, and 54 is a key storage bag! (KS), 55 represents a main storage device.

Regarding the memory protection of the main memory device 55 in such a multiprocessing system, the TLBs indicated by 52-1 to 52-n contain information of a copy of the "key" corresponding to the real address, and a certain processor When accessing the storage device 55, it is checked whether the information on the copy of the "key" in the TLB entry for the corresponding real address matches the PSW key held by the processor, and whether access is permitted or not is determined based on the result.

By the way, in a system having a plurality of processors 51-1 to 51-n, a certain processor may rewrite the contents of the "key" storage device 54 in the process of data processing, and in this case, the same address held by a capable processor may be rewritten. A copy of the 1 key 1 information in the TLB entry for the 1 key is invalid.

In a conventional multiprocessing system, when the contents of the "key" storage device 54 are rewritten, copies of the "1 key" information for the same address in the TLBs 52-1 to 52-n in each processor are invalidated. Therefore, for each processor 51-1 to 51-n, TLB
Invalidation request signals (referred to as PPTLB requests) S-1 to S-
n and the corresponding real address are sent to the processor on the bus signal line at -1 to 10.

When each processor 51-1 to 51-n receives the PPTLB request S-L to S-n, the processor 51-1 to 51-n
The contents in ~52-n are read out sequentially, and if there is a matching address, that TLB entry is invalidated.

[Problem to be solved by the invention]

In conventional multiprocessing systems, each processor has P
Since the address sent with the PTLB request is a real address, each processor sequentially reads the contents of the TLB entries to see if there is a match, and if there is a match, invalidates that entry.

In this method, it is unknown whether the real address is in a TLB entry or not, so all TLB entries are always
It is necessary to read J and perform verification. However, in general, each processor executes a different task, and it is rare for the same real address to be entered in different TLBs, so it is wasteful to read and check all TLB entries as described above. This also imposes an unnecessarily large processing burden on each processor. In the conventional example,
In order to solve the above problem, when the "key" memory contents are rewritten, the TLB entry can be read and verified (
In order to quickly decide whether or not to perform a TLB search,
TLB en) It was necessary to provide a dedicated hardware device to perform inverse conversion of IJ.

The present invention was made in view of the above-mentioned problems, and
It is possible to quickly decide whether or not to perform a TLB search with only a small amount of hardware addition, without having to install a special dedicated hardware device for processing PTLB requests.
The purpose is to provide a "key" information processing device.

[Means to solve the problem]

According to the invention, the above-mentioned object is achieved by the means specified in the claims.

That is, the present invention has a plurality of processors that share a main memory, and the processor is provided with a memory (TLB) that stores a correspondence table for rapidly converting virtual addresses to real addresses.
In addition, in the TLB above, there is a “key” corresponding to the real address.
When a copy of the information is registered and the processor accesses the main memory, it uses a copy of the "key" in the TLB and the PSW key held by Bromo 1. ji, in a multi-processing computer system that recognizes the coincidence of "keys", means for recording read operations of each processor for each "key" information in the key storage device in the main controller; When the "key" information in the storage device is rewritten, the processor that read the "key" is confirmed using the recording means, and the key is rewritten only for the processor that read the "key". When converting a logical address into a real address, the "key" information processing method processor of the multiprocessing system is characterized in that it is provided with a means for notifying the user. Use the contents of TLB, and if it does not exist (T
LB miss), the real address is determined by dynamic address translation (DAT), and the contents of the "key" storage of the real address are read out and a copy of the "key" is registered in the TLB.

When a "key" is read due to this TLB error, the main controller sets and records a flag corresponding to the read processor in a flag register provided in addition to the "key" storage device.

Next, when a one-key one-by-one rewrite is performed on the "key" storage device by a certain processor, the processor simultaneously reads the contents of the flag register corresponding to the "key" and holds a copy of the "key" in the TLB. only to be notified that the copy of the “key” is no longer valid.

〔Example〕

FIG. 1 shows a configuration diagram of a multiprocessing system to which the present invention is applied, and in the figure, 1-1 to 1-ports are processors;
2-1 to 2-n are TLBs in each processor; 3 is a main controller; 4 is a key storage device (KS); 5 is a main storage device; alphabetical groups a-1 to a-n are PPTLB request signal lines; b-1x
bn represents a bus signal line to each processor.

In the figures, parts not related to the present invention are omitted for clarity of the drawings. The configuration of FIG. 1 is the same as the configuration explained in the prior art section except for parts related to the present invention, and detailed explanation will be omitted. The following embodiments are constructed in connection with the "key" storage device 4.

FIG. 2 shows a circuit block diagram of an embodiment of the present invention,
6-1 to 6-n are buffer registers corresponding to processors 1-1 to 1-n, respectively, 7 is a priority circuit, 8 is a buffer register for holding the output of the priority circuit, and 9 is a "key" read operation. 10 is a flag write control circuit, 11 is a PPTLB request control circuit, L2
-'L~12-n are buffer registers for holding PPTLB addresses for each processor 1-1~1-n, alphabetical groups c-1~G-11 are bus signal lines connected to each processor, d-1~ d-n is a PPTLB request signal line to each processor, and e-L to e-n are PPTL lines to each processor.
B is a request address signal line, f is an address signal line, g is a control signal line, and h is a data signal line for reading and writing a "key".

The configuration and operation of this embodiment will be explained below.

Access to the "key" storage bags [24] of the processors 1-1 to l-n is performed using a priority system that gives access priority to the buffer registers 6-1 to 6-n and each processor l-1 to l-1-n. This is done via a circuit 7 and a buffer register 8.

One "key" is assigned to the "key" storage device 4 corresponding to one page in the main memory, and a copy of the "key" is included in the TLB entry of each processor.

The key storage device 4 is provided with a flag register 9 for storing and holding the "key" read operation from each processor, and its write control circuit 10.
It is recorded whether the "key" has been read.

When the "key" contents are rewritten in an existing processor, the contents of the flag register 9 are read out and the PPT
The LB control circuit 11 sends a PPTLB request to the signal line d only to the processor that has read the contents of the "key" in the past.
-1 to dn.

Further, the address of the rewritten "key" information is sent to each processor by signals *a-1 to e- as a PPTLB address via the address signal line f and buffer registers 12-1 to 12-n.

FIG. 3 shows a block diagram of the flag write control circuit 10 to the flag register 9. In the figure, 8-1 is a valid bit, 8-2 is a function bit, and 8-3 is an ID.
, 8-4 is an address, 8-5 is data, 13 is a function decoder, 14 is an ID decoder, 16-1~
16-n represents an AND circuit, the letter 1 represents a flag write enable signal line, and 1d-1 to 1d-n represent processor number selection lines.

Other symbols are the same as in FIG.

The buffer register 8 connected to the priority circuit 7 has the following bit configuration: valid bit 8-1, function bit 8-2, ID...8-3, address 8-4, data 8.
-5.

Further, the flag register 9 has a matrix-like bit configuration with the address 8-4 to the "key" storage device in the row direction and the number n of processors in the system in the column direction.

Now, to explain the flag writing operation when a certain processor reads a "key" in the "key" storage device, the address of the "key" storage device read by a certain processor is the address in the buffer register 8, -4, address valid bit 8-1, function 8-
2. The function data 13 and the AND circuit 15 check the write permission to the flag register 9, and the D bit 8-3 and the ID decoder 14 check the "key"
The number of processors that read the storage device is identified;
One line in the signals m1d-1 to 1d-n becomes valid,
The logical product with the write permission signal line 1 is an AND circuit 16-1.
~16-n, and a flag is set in the corresponding bit.

Next, the operation when the "key" is rewritten will be explained.

FIG. 4 shows a block diagram of the PPTLB control circuit 11, in which 17 is an AND circuit, and 18-1 to 18-n are N circuits.

T circuit, 19-1 to 19-n are AND circuits (3-man power),
20-1 to 20- are flip 70 tubes (FF), and alphabetical characters "-1 to j-n" represent read signal lines of the flag register.

Other symbols are the same as in FIGS. 2 and 3.

If a certain processor rewrites the “key”,
The function 8-2 of the buffer register 8 determines a key rewrite request (SSK request) by the decoder 13, and performs a logical product with the valid bit 8-1 by the AND circuit 17 to check its validity. Also, ID decoder 1
4. The number of the processor other than the SSK request source is selected by the NOT circuits 18-1 to 18-n, and the contents of the flag register 9 indexed by the address 8-4 in the register 8 are set to the signal line j-1=j. -n, AND circuit 1
9-1 to 19-n and flip 70 knobs 20-1 to 20
- By ◯, the PPTLB request is sent through signal lines d-1 to d-n only to the processor whose flag is set and not to the processor that ultimately becomes the SSK request source. At the same time, all flags in the flag register 9 indexed by the address 8-4 of the "key" are cleared and returned to the initial state.

The processor that receives the PPTLB request is likely to have a copy of the "key" related to the SSK request in the TLB entry, so only that processor will search the TLB contents and if a match is found. Invalidate that TLB entry.

〔Effect of the invention〕

When a “key” is rewritten, only the processor that holds a copy of the “key” in the TLB needs to perform a TLB search; It contains a copy of the same real address and its "key", and it is rare for another processor to rewrite the "key", and most of the TLB searches that were conventionally performed can be omitted, resulting in significant processing efficiency. can be improved.

[Brief explanation of the drawing]

Fig. 1 is a block diagram of a multiprocessing system to which the present invention is applied, Fig. 2 is a circuit block diagram of an embodiment of the present invention, Fig. 3 is a block diagram of a flag writing circuit, and Fig. 4 is a PPTLB.
A block diagram of the request control circuit, and FIG. 5 is a configuration diagram of a multiprocessing system. 1-1~l-n... Processor, 2-1~2-
n...TLB, 3...Main controller, 4
..."Key" storage device (KS), 5...
・Main storage device, 6-1 to 6-n...Buffer register, 7...Priority circuit, 8...Buffer register, 9...Flag register, 10
...Write control circuit, 11...PPT
LB request 10...Write control circuit, 11...
... PPTLB request control circuit, 12-1 to 12-n.
... Buffer register, 13 ... Function decoder, 14 ... ID decoder, 1
5. 16-1 to 16-n, 17. 19-1~19
-n・-・-・-AND circuit, 18-1 to 18-n--
N OT circuit, 20-1 to 20-1... flip-flop, a-1 to a-n... PPTLB request signal, b-1 to b-n... Bus signal line to each processor, c-1 to c-n...Bus signal line to each processor, d-1=d-n...PPTL
B request signal line, e-1 to e-n...PPTLB
Request address signal line, f...address signal line,
g...Control word line, h...Data signal line, i...Flag write permission signal line, 1d-1
〜1d-n...Processor number selection signal line,''
-1~j-n...Flag register read signal line

Claims (1)

[Scope of Claims] A plurality of processors sharing a main storage device are provided, and each processor is provided with a TLB storing a correspondence table for rapidly converting a virtual address to a real address, and the TLB described above is provided.
A copy of the key information corresponding to the real address is registered in the LB, and when the processor accesses the main memory,
In a multi-processing computer system that verifies the coincidence of a key between a copy of the key in the TLB and key information held by the processor, the main controller includes a controller for each processor for each key information in the key storage device. A means for recording key read operations for TLB registration, and when key information in the key storage device is rewritten,
A multi-processing system characterized by comprising means for confirming the processor that read the key using the recording means and for notifying only the processor that read the key that the key has been rewritten. Key information processing method.