JPS6083156A - バツフアストレ−ジ制御方式 - Google Patents

バツフアストレ−ジ制御方式

Info

Publication number
JPS6083156A
JPS6083156A JP58191616A JP19161683A JPS6083156A JP S6083156 A JPS6083156 A JP S6083156A JP 58191616 A JP58191616 A JP 58191616A JP 19161683 A JP19161683 A JP 19161683A JP S6083156 A JPS6083156 A JP S6083156A
Authority
JP
Japan
Prior art keywords
block
sub
storage
buffer storage
tag
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP58191616A
Other languages
English (en)
Japanese (ja)
Other versions
JPH0259493B2 (enExample
Inventor
Masahiro Kuriyama
栗山　正裕
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP58191616A priority Critical patent/JPS6083156A/ja
Publication of JPS6083156A publication Critical patent/JPS6083156A/ja
Publication of JPH0259493B2 publication Critical patent/JPH0259493B2/ja
Granted legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
    • G06F12/0844—Multiple simultaneous or quasi-simultaneous cache accessing

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Memory System Of A Hierarchy Structure (AREA)
JP58191616A 1983-10-13 1983-10-13 バツフアストレ−ジ制御方式 Granted JPS6083156A (ja)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP58191616A JPS6083156A (ja) 1983-10-13 1983-10-13 バツフアストレ−ジ制御方式

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP58191616A JPS6083156A (ja) 1983-10-13 1983-10-13 バツフアストレ−ジ制御方式

Publications (2)

Publication Number Publication Date
JPS6083156A true JPS6083156A (ja) 1985-05-11
JPH0259493B2 JPH0259493B2 (enExample) 1990-12-12

Family

ID=16277594

Family Applications (1)

Application Number Title Priority Date Filing Date
JP58191616A Granted JPS6083156A (ja) 1983-10-13 1983-10-13 バツフアストレ−ジ制御方式

Country Status (1)

Country Link
JP (1) JPS6083156A (enExample)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS62118456A (ja) * 1985-11-19 1987-05-29 Nec Corp キヤツシユメモリ
JPH0290348A (ja) * 1988-09-28 1990-03-29 Nec Corp データ無効化サイズ可変なキャッシュメモリシステム
JP2010055273A (ja) * 2008-08-27 2010-03-11 Nec Corp キャッシュメモリ装置及びその制御方法

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS57167188A (en) * 1981-04-06 1982-10-14 Nippon Telegr & Teleph Corp <Ntt> Buffer memory controlling system

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS57167188A (en) * 1981-04-06 1982-10-14 Nippon Telegr & Teleph Corp <Ntt> Buffer memory controlling system

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS62118456A (ja) * 1985-11-19 1987-05-29 Nec Corp キヤツシユメモリ
JPH0290348A (ja) * 1988-09-28 1990-03-29 Nec Corp データ無効化サイズ可変なキャッシュメモリシステム
JP2010055273A (ja) * 2008-08-27 2010-03-11 Nec Corp キャッシュメモリ装置及びその制御方法

Also Published As

Publication number Publication date
JPH0259493B2 (enExample) 1990-12-12

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