JPH0213499B2 - - Google Patents

Info

Publication number
JPH0213499B2
JPH0213499B2 JP59172031A JP17203184A JPH0213499B2 JP H0213499 B2 JPH0213499 B2 JP H0213499B2 JP 59172031 A JP59172031 A JP 59172031A JP 17203184 A JP17203184 A JP 17203184A JP H0213499 B2 JPH0213499 B2 JP H0213499B2
Authority
JP
Japan
Prior art keywords
signal
read
active system
address counter
circuit
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
JP59172031A
Other languages
English (en)
Japanese (ja)
Other versions
JPS6150435A (ja
Inventor
Hisashi Naito
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Mitsubishi Electric Corp
Original Assignee
Mitsubishi Electric Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Mitsubishi Electric Corp filed Critical Mitsubishi Electric Corp
Priority to JP59172031A priority Critical patent/JPS6150435A/ja
Priority to FR858512508A priority patent/FR2569323B1/fr
Priority to US06/767,192 priority patent/US4821227A/en
Publication of JPS6150435A publication Critical patent/JPS6150435A/ja
Publication of JPH0213499B2 publication Critical patent/JPH0213499B2/ja
Granted legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L1/00—Arrangements for detecting or preventing errors in the information received
    • H04L1/22—Arrangements for detecting or preventing errors in the information received using redundant apparatus to increase reliability
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04J—MULTIPLEX COMMUNICATION
    • H04J3/00—Time-division multiplex systems
    • H04J3/02—Details
    • H04J3/06—Synchronising arrangements
    • H04J3/062—Synchronisation of signals having the same nominal but fluctuating bit rates, e.g. using buffers
    • H04J3/0626—Synchronisation of signals having the same nominal but fluctuating bit rates, e.g. using buffers plesiochronous multiplexing systems, e.g. plesiochronous digital hierarchy [PDH], jitter attenuators
    • H04J3/0629—Synchronisation of signals having the same nominal but fluctuating bit rates, e.g. using buffers plesiochronous multiplexing systems, e.g. plesiochronous digital hierarchy [PDH], jitter attenuators in a network, e.g. in combination with switching or multiplexing, slip buffers

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Signal Processing (AREA)
  • Computer Hardware Design (AREA)
  • Synchronisation In Digital Transmission Systems (AREA)
  • Detection And Prevention Of Errors In Transmission (AREA)
  • Time-Division Multiplex Systems (AREA)
JP59172031A 1984-08-18 1984-08-18 プレジオクロナス整合装置 Granted JPS6150435A (ja)

Priority Applications (3)

Application Number Priority Date Filing Date Title
JP59172031A JPS6150435A (ja) 1984-08-18 1984-08-18 プレジオクロナス整合装置
FR858512508A FR2569323B1 (fr) 1984-08-18 1985-08-19 Dispositif d'adaptation plesiochrone
US06/767,192 US4821227A (en) 1984-08-18 1985-08-19 Plesiochronous matching apparatus

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP59172031A JPS6150435A (ja) 1984-08-18 1984-08-18 プレジオクロナス整合装置

Publications (2)

Publication Number Publication Date
JPS6150435A JPS6150435A (ja) 1986-03-12
JPH0213499B2 true JPH0213499B2 (enExample) 1990-04-04

Family

ID=15934244

Family Applications (1)

Application Number Title Priority Date Filing Date
JP59172031A Granted JPS6150435A (ja) 1984-08-18 1984-08-18 プレジオクロナス整合装置

Country Status (3)

Country Link
US (1) US4821227A (enExample)
JP (1) JPS6150435A (enExample)
FR (1) FR2569323B1 (enExample)

Families Citing this family (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
FR2600474B1 (fr) * 1986-06-18 1988-08-26 Alcatel Thomson Faisceaux Procede de synchronisation de deux trains binaires
US4922438A (en) * 1986-12-11 1990-05-01 Siemens Aktiengesellschaft Method and apparatus for reading packet-oriented data signals into and out of a buffer
JP2875287B2 (ja) * 1989-07-19 1999-03-31 株式会社日立製作所 フレームアライナおよびその制御方法
JP2806657B2 (ja) * 1991-09-26 1998-09-30 日本電気株式会社 プレジオクロナス／ドップラーバッファとプレジオクロナス同期／ドップラー効果抑圧方法
US5617088A (en) 1994-01-26 1997-04-01 Sony Corporation Sampling frequency converting device and memory address control device
US5872823A (en) * 1997-04-02 1999-02-16 Sutton; Todd R. Reliable switching between data sources in a synchronous communication system
US6389553B1 (en) * 1998-05-26 2002-05-14 Nortel Networks Limited Redundant link delay maintenance circuit and method
CN1299464C (zh) * 2003-06-04 2007-02-07 中兴通讯股份有限公司 在同步系统中实现时钟主备用的方法和装置
JP4852963B2 (ja) * 2005-10-14 2012-01-11 株式会社日立製作所 伝送装置

Family Cites Families (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3909795A (en) * 1973-08-31 1975-09-30 Gte Automatic Electric Lab Inc Program timing circuitry for central data processor of digital communications system
FR2320023A1 (fr) * 1975-07-28 1977-02-25 Constr Telephoniques Procede et dispositif de resynchronisation d'informations entrantes structurees en trames
US4358823A (en) * 1977-03-25 1982-11-09 Trw, Inc. Double redundant processor
GB2066627B (en) * 1979-12-13 1983-12-07 Plessey Co Ltd Pcm frame aligner with frame slip characteristic
US4387394A (en) * 1980-12-31 1983-06-07 Rca Corporation Sensing focus of a color kinescope
US4429386A (en) * 1981-01-05 1984-01-31 Siemens Corporation Buffer arrangement of a PCM exchange system

Also Published As

Publication number Publication date
JPS6150435A (ja) 1986-03-12
FR2569323B1 (fr) 1989-05-05
US4821227A (en) 1989-04-11
FR2569323A1 (fr) 1986-02-21

Similar Documents

Publication Publication Date Title
JPS62227243A (ja) 伝送制御方式
JPH0213499B2 (enExample)
US4823365A (en) Synchronization method and elastic buffer circuit
US4314109A (en) Synchronization system for key telephone system
JP2550083B2 (ja) パケット交換網における呼の迂回方法
JPS615363A (ja) 共有メモリの制御装置
JP3199418B2 (ja) データレート変換装置
JPH04371096A (ja) 位相同期検出方式
JP3229993B2 (ja) フレームパルス切替回路
JP3040316B2 (ja) 冗長系伝送路の終端回路
JP2701741B2 (ja) 二重化・一重化切替方式
JPH02122317A (ja) クロック切り替え制御方式
JPH0528538B2 (enExample)
JPS60254846A (ja) Ｃｄｔ装置の回線切替方式
JPS6160010A (ja) 先発優先回路
JP2663487B2 (ja) デジタル通信装置
JPS6184136A (ja) スリツプ制御回路
JPS62128249A (ja) 交換機外部監視装置による監視方式
JPS60246200A (ja) プレジオクロナス整合回路装置
JPS6271366A (ja) デイジタルハイウエイの２重化・１重化切替方式
JPH027240B2 (enExample)
JPH04304737A (ja) 多重伝送方式のフェイルセーフ方法
JPS59123026A (ja) 非同期バスにおける応答信号出力方式
JPH04304725A (ja) 伝送路切替方式
JPH01109833A (ja) データ分岐装置