JP7235683B2 - ハードマスク及びその他のパターニング応用のための高密度低温炭素膜 - Google Patents
ハードマスク及びその他のパターニング応用のための高密度低温炭素膜 Download PDFInfo
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- JP7235683B2 JP7235683B2 JP2019567614A JP2019567614A JP7235683B2 JP 7235683 B2 JP7235683 B2 JP 7235683B2 JP 2019567614 A JP2019567614 A JP 2019567614A JP 2019567614 A JP2019567614 A JP 2019567614A JP 7235683 B2 JP7235683 B2 JP 7235683B2
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Images
Classifications
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- H10B43/23—EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels
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Description
集積回路は、単一チップ上に数百万個ものトランジスタ、コンデンサ、及び抵抗器が含まれうる、複雑なデバイスへと進化を遂げている。チップ設計の進化には、より高速な回路及びより高い回路密度が、継続的に必要になる。より高い回路密度を有する高速回路を求める需要により、かかる集積回路の製造に使用される材料についても、相応の要求が課されている。具体的には、集積回路構成要素の寸法がサブミクロン単位まで小さくなるにつれ、かかる構成要素から好適な電気的性能を得るために、低抵抗率の導電性材料だけでなく低誘電率の絶縁材料を使用することも、現在必要になっている。
以下の非限定的な例は、本書に記載の実行形態を更に例示するために提供されている。しかし、これらの例は、本書に記載の実行形態の全てを網羅することを意図しておらず、その範囲を限定するためのものでもない。
極紫外(EUV)パターンニング方式において金属含有フォトレジストを使用する場合、半導体デバイスにおける極小不具合(例えばブリッジ形成の欠陥及び間隔形成の欠陥)を防止するために、下層の選択が重要になる。EUVパターニング(リソグラフィ)方式向けの従来的な下層は、スピンオンカーボン(SOC)材料である。しかし、パターンニング中に、スズなどの金属は、例えばSOC材料を通って拡散し、半導体デバイスの極小不具合につながる。かかる極小不具合は、半導体性能を引き下げ、劣化させ、妨害するよう作用する。
1)堆積時の膜中の炭素原子の総量に基づいて少なくとも40、45、50、55、60、65、70、75、80、又は85パーセントである、sp3混成炭素原子の質量/パーセンテージ(すなわち、sp3混成炭素原子の含有量)であって、上記の又はその他の実行形態では、堆積時の膜中の炭素原子の総量に基づいて最大で45、50、55、60、65、70、75、80、85、又は90パーセントとなり、上記の又はその他の実行形態では、堆積時の膜中の炭素原子の総量に基づいて約50~約90パーセント(例えば約60~約70パーセント)となる、sp3混成炭素原子の質量/パーセンテージ、
2)約5Å~約20,000Å(例えば約300Å~約5000Å、例としては約2000Å~約3000Å)である厚さであって、あるいは約5Å~約200Åである、厚さ、
3)2.0を上回る(例えばおよそ2.0~およそ3.0の、例としては2.3の)屈折率又はn値(633nmにおけるn)、
4)0.1を上回る(例えばおよそ0.2~およそ0.3の、例としては0.25の)吸光係数又はk値(633nmにおけるk)、
5)応力(MPa)であって、約-300MPaを下回る(例えばおよそ-600MPa~およそ-300MPa、およそ-600MPa~およそ-500MPaの、例としてはおよそ-550MPaの)応力、
6)密度(g/cc)であって、1.8g/ccを上回る(例えばおよそ2.0g/cc以上、およそ2.5g/cc以上の、例としては約1.8g/cc~約2.5g/ccの)密度、
7)弾性率(GPa)であって、150GPaを上回る(例えば約200~約400GPa)の弾性率、という特性のうちの、一又は複数を有する。
Claims (13)
- 基板を処理する方法であって、
静電チャック上に基板が位置付けられている、プロセスチャンバの処理空間内に、炭化水素を含有する混合ガスを流入させることであって、前記基板が0.5mTorr~10Torrの圧力において維持される、混合ガスを流入させることと、
前記基板上にダイヤモンド状炭素膜を堆積させるために、前記静電チャックに第1RFバイアスを印加することにより前記基板の水平面においてプラズマを生成することであって、前記ダイヤモンド状炭素膜が、1.8g/ccを上回る密度と、応力の絶対値が500よりも小さい応力であって、-500MPaを下回る応力とを有し、前記ダイヤモンド状炭素膜が、50パーセント~90パーセントのsp 3 混成炭素原子を含有し、前記基板が10℃~50℃の温度に維持される、プラズマを生成することとを含む、方法。 - 前記基板の水平面においてプラズマを生成することが、前記静電チャックに第2RFバイアスを印加することを更に含む、請求項1に記載の方法。
- 前記第1RFバイアスは、350KHz~100MHzの周波数で、10ワット~3000ワットの電力で提供される、請求項2に記載の方法。
- 前記第1RFバイアスは、13.56MHzの周波数で、2500ワット~3000ワットの電力で提供される、請求項3に記載の方法。
- 前記第2RFバイアスは、350KHz~100MHzの周波数で、10ワット~3000ワットの電力で提供される、請求項4に記載の方法。
- 前記第2RFバイアスは、2MHzの周波数で、800ワット~1200ワットの電力で提供される、請求項5に記載の方法。
- 前記静電チャック上に位置付けられた前記基板にチャック電圧を印加することを更に含む、請求項1に記載の方法。
- 前記ダイヤモンド状炭素膜が150GPaを上回る弾性率を有する、請求項1に記載の方法。
- 前記炭化水素を含有する混合ガスが、C2H2、C3H6、CH4、C4H8、1,3-ジメチルアダマンタン、ビシクロ[2.2.1]へプタ-2,5-ジエン(2,5-ノルボルナジエン)、アダマンタン(C10H16)、ノルボルネン(C7H10)、及びこれらの組み合わせ、からなる群から選択された炭化水素前駆体を含む、請求項1に記載の方法。
- 前記炭化水素を含有する混合ガスが、He、Ar、Xe、N2、H2、及びこれらの組み合わせ、からなる群から選択された希釈ガスを更に含む、請求項9に記載の方法。
- 基板を処理する方法であって、
静電チャック上に基板が位置付けられている、プロセスチャンバの処理空間内に、炭化水素を含有する混合ガスを流入させることであって、前記静電チャックはチャック電極と前記チャック電極から離れたRF電極を有し、前記基板が0.5mTorr~10Torrの圧力において維持され、前記炭化水素を含有する混合ガスがアセチレン(C2H2)を含む、混合ガスを流入させることと、
前記基板上にダイヤモンド状炭素膜を堆積させるために、前記RF電極に第1RFバイアスを印加し、前記チャック電極に第2RFバイアスを印加することにより前記基板の水平面においてプラズマを生成することであって、前記ダイヤモンド状炭素膜が、1.8g/cc~2.5g/ccの密度と、-600MPa~-300MPaの応力とを有する、プラズマを生成することとを含む、方法。 - 前記第1RFバイアスは、13.56MHzの周波数で、2500ワット~3000ワットの電力で提供され、前記第2RFバイアスは、2MHzの周波数で、800ワット~1200ワットの電力で提供される、請求項11に記載の方法。
- 前記ダイヤモンド状炭素膜が、極紫外(EUV)リソグラフィプロセスにおいて下層として使用される、請求項11に記載の方法。
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