CN112740360A - 用于图案化应用的高密度碳膜 - Google Patents

用于图案化应用的高密度碳膜 Download PDF

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Publication number
CN112740360A
CN112740360A CN201980061362.2A CN201980061362A CN112740360A CN 112740360 A CN112740360 A CN 112740360A CN 201980061362 A CN201980061362 A CN 201980061362A CN 112740360 A CN112740360 A CN 112740360A
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China
Prior art keywords
substrate
bias
watts
electrostatic chuck
frequency
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CN201980061362.2A
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Inventor
E·文卡塔苏布磊曼聂
S·E·戈特海姆
P·曼纳
A·B·玛里克
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Applied Materials Inc
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Applied Materials Inc
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    • H01L21/02225—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
    • H01L21/0226—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process
    • H01L21/02263—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase
    • H01L21/02271—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase deposition by decomposition or reaction of gaseous or vapour phase compounds, i.e. chemical vapour deposition
    • H01L21/02274—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase deposition by decomposition or reaction of gaseous or vapour phase compounds, i.e. chemical vapour deposition in the presence of a plasma [PECVD]
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    • H01L21/0334—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane
    • H01L21/0337—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane characterised by the process involved to create the mask, e.g. lift-off masks, sidewalls, or to modify the mask, e.g. pre-treatment, post-treatment
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    • G03—PHOTOGRAPHY; CINEMATOGRAPHY; ANALOGOUS TECHNIQUES USING WAVES OTHER THAN OPTICAL WAVES; ELECTROGRAPHY; HOLOGRAPHY
    • G03F—PHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES, e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTOR DEVICES; MATERIALS THEREFOR; ORIGINALS THEREFOR; APPARATUS SPECIALLY ADAPTED THEREFOR
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    • G03F7/2004—Exposure; Apparatus therefor with visible light or UV light, through an original having an opaque pattern on a transparent support, e.g. film printing, projection printing; by reflection of visible or UV light from an original such as a printed image characterised by the use of a particular light source, e.g. fluorescent lamps or deep UV light
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Abstract

本公开的实施例总体上涉及用于图案化应用的高透明、高密度的碳膜的沉积。在一个实施例中，提供一种在基板上形成碳膜的方法。所述方法包括：使含碳氢化合物的气体混合物流入工艺腔室中，所述工艺腔室具有定位在静电吸盘上的基板，其中将基板保持在约‑10℃至约20℃的温度和约0.5毫托至约10托的腔室压力；以及通过将第一RF偏压施加至静电吸盘来生成等离子体，以在基板上沉积含有约60％或更多的杂化sp3原子的类金刚石碳膜，其中所述第一RF偏压是以约1800瓦至约2200瓦的功率和约40MHz至约162MHz的频率提供。

Description

用于图案化应用的高密度碳膜
背景技术
技术领域
本公开的实施例总体上涉及集成电路的制造。更具体而言，本文描述的实施例提供用于图案化应用的高密度碳膜的沉积的技术。
相关技术说明
集成电路已经发展成为复杂器件，所述器件可在单个芯片上包括数百万个晶体管、电容器和电阻器。芯片设计的发展持续需要更快的电路系统和更大的电路密度。针对具有更大电路密度的更快电路的需求对集成电路部件制造中所使用的工艺序列提出了相应的要求。例如，在使用常规光刻技术的工艺序列中，在设置在基板上的材料层的堆叠之上形成能量敏感的抗蚀剂层。将能量敏感的抗蚀剂层暴露于图案的影像以形成光致抗蚀剂(photoresist)掩模。此后，使用蚀刻工艺将掩模图案转移到堆叠的一个或多个材料层。
随着图案尺寸减小，能量敏感的抗蚀剂的厚度相应地减小，以便控制图案的分辨率。由于化学蚀刻剂的侵蚀，此类薄抗蚀剂层可能不足以在图案转移操作期间掩盖下面的材料层。因为硬掩模对化学蚀刻剂有更大的抵抗力，所以通常在能量敏感抗蚀剂层与下面的材料层之间使用硬掩模以促进图案转移。随着临界尺寸(CD)减小，当前的硬掩模材料欠缺相对于下面的材料(例如，氧化物和氮化物)的期望的蚀刻选择性并且通常难以沉积。
因此，在本领域中需要改进的硬掩模层和用于沉积改进的硬掩模层的方法。
发明内容
本公开的实施例总体上涉及集成电路的制造。更具体而言，本文描述的实施例提供用于图案化应用的高密度膜的沉积的技术。在一个实施例中，提供一种在基板上形成碳膜的方法。所述方法包括：使含碳氢化合物的气体混合物流入具有定位在静电吸盘上的基板的工艺腔室中，其中基板保持在约-10℃至约20℃的温度和约0.5毫托至约10托的腔室压力；以及通过将第一RF偏压施加至静电吸盘来生成等离子体，以在基板上沉积含有约60％或更多的杂化(hybridized)sp3原子的类金刚石碳膜，其中第一RF偏压是以针对300mm基板的约1800瓦至约2200瓦的功率和约40MHz至约162MHz的频率提供。
在另一实施例中，所述方法包括：使含碳氢化合物的气体混合物流入具有定位在静电吸盘上的基板的工艺腔室的处理空间；以及通过将第一RF偏压施加至静电吸盘以及将第二RF偏压施加至设置在静电吸盘上方且相对的电极来生成等离子体，以在基板上沉积类金刚石碳膜，其中第一RF偏压是以约13.56MHz或更低的频率提供，并且第二RF偏压是以约40MHz或更高的频率提供，并且基板保持在约-10℃至约20℃的温度和约0.5毫托至约10托的腔室压力。
在又另一实施例中，所述方法包括：使含碳氢化合物的气体混合物流入具有定位在静电吸盘上的基板的工艺腔室的处理空间中，其中基板保持在约5毫托之间的压力，并且其中含碳氢化合物的气体混合物包括乙炔(C2H2)；通过将第一RF偏压施加至静电吸盘来在基板水平(level)处生成等离子体，以在基板上沉积类金刚石碳膜，其中第一RF偏压是以在约2000瓦之间的功率和约60MHz的频率提供；在类金刚石碳膜之上形成图案化的光致抗蚀剂层；以对应于所图案化的光致抗蚀剂层的图案来蚀刻类金刚石碳膜；使图案蚀刻到基板中；以及将材料沉积至类金刚石碳膜的所蚀刻的部分中。
附图说明
为了可详细地理解本公开的上述特征的方式，可参考实施例来对上文简要概述的实施例进行更具体的描述，这些实施例中的一些在附图中示出。然而，应注意，附图仅示出本公开的典型实施例，因此不应被认为是对本公开的范围的限制，因为本公开可以允许其他等效的实施例。
图1A描绘可用于实施本文描述的实施例的沉积系统的示意性截面图；
图1B描绘可用于实施本文描述的实施例的另一沉积系统的示意性截面图；
图2描绘可用在图1A和图1B的设备中以实施本文所述的实施例的静电吸盘的示意性截面图；
图3描绘根据本公开的一个或多个实施例的用于在设置在基板上的膜堆叠上形成类金刚石碳层的方法的流程图；
图4A至图4B描绘根据本公开的一个或多个实施例的用于在形成在基板上的膜堆叠上形成类金刚石碳层的序列的一个实施例；
为便于理解，在可能的情况下使用相同的附图标记来指示附图中共有的相同元件。预期一个实施例中的元件与特征可有益地并入其他实施例中，而无需进一步叙述。
具体实施方式
以下的本公开内容描述用于在基板上沉积类金刚石碳膜的技术。下文将会参考可使用任何适合的薄膜沉积系统执行的PECVD工艺来描述本文所述的实施例可。适合的系统的示例包括可使用
Figure BDA0002982682580000031
处理腔室的
Figure BDA0002982682580000032
系统、PRECISION
Figure BDA0002982682580000033
系统、
Figure BDA0002982682580000034
系统、
Figure BDA0002982682580000035
GTTM系统、
Figure BDA0002982682580000036
XP PrecisionTM系统、
Figure BDA0002982682580000037
SETM系统、
Figure BDA0002982682580000038
处理腔室、以及MesaTM处理腔室，所有上述系统/腔室都可从美国加利福尼亚州圣克拉拉市(Santa Clara)的应用材料公司购得。可执行PECVD工艺的其他工具也可以适配成受益于本文所述的实施例。此外，可可有利地使用实现本文所述的PECVD工艺的任何系统。本文描述的设备描述是说明性的，并且不应被理解或解释为限制本文描述的实施例的范围。
图1A描绘根据本文描述的实施例的可用于执行类金刚石碳层沉积的基板处理系统132的示意图。基板处理系统132包括工艺腔室100，所述工艺腔室100耦接至气体面板130和控制器110。工艺腔室100通常包括限定处理空间126的顶壁124、侧壁101和底壁122。基板支撑组件146设置在工艺腔室100的处理空间126中。基板支撑组件146通常包括由轴杆160支撑的静电吸盘150。静电吸盘150通常可以由铝、陶瓷、和其他适合的材料(诸如不锈钢)制成。可以使用位移机构(未示出)使静电吸盘150在工艺腔室100内在垂直方向上移动。
真空泵102耦接在工艺腔室100的底部中形成的端口。真空泵102用于保持在工艺腔室100中保持期望的气压。真空泵102也从工艺腔室100排出后处理气体以及工艺的副产物。
具有多个孔隙128的气体分配组件120设置在工艺腔室100的顶部上、在静电吸盘150上方。气体分配组件120的孔隙128用于将工艺气体引入工艺腔室100中。孔隙128可以具有不同的尺寸、数量、分布、形状、设计和直径，以促进用于不同工艺要求的各种工艺气体的流动。气体分配组件120连接气体面板130，气体面板130允许各种气体在处理期间流到处理空间126。等离子体由离开气体分配组件120的工艺气体混合物形成，以增强工艺气体的热分解，从而造成材料沉积在定位在静电吸盘150上的基板190的顶表面191上。
气体分配组件120和静电吸盘150可以在处理空间126中形成一对间隔开的电极。一个或多个RF电源140通过匹配网络138(匹配网络138是可选的)提供偏压电位给气体分配组件120，以促进在气体分配组件120与静电吸盘150之间生成等离子体。替代地，RF电源140和匹配网络138可耦接至气体分配组件120、静电吸盘150、或耦接至气体分配组件120和静电吸盘150两者、或者耦接至设置在工艺腔室100外部的天线(未示出)。在一些实施例中，RF电源140可以以350KHz、2MHz、13.56MHz、27MHz、40MHz、60MHz、100MHz或162MHz的频率产生功率。
控制器110包括中央处理单元(CPU)112、存储器116、以及用于控制工艺序列并且调控来自气体面板130的气流的支持电路114。CPU 112可以是任何形式的可以在工业设置中使用的通用计算机处理器。可以将软件例程储存在存储器116(诸如随机存取存储器、只读存储器、软盘、或硬盘驱动器、或其他形式的数字储存)中。支持电路114耦接至CPU 112，并且可包括高速缓存、时钟电路、输入/输出系统、电源等等。控制器110与基板处理系统132的各种部件之间的双向通信通过被统称为信号总线118的大量信号缆线来处理，信号总线118中的一些在图1A中示出。
图1B描绘可用于实施本文所述实施例的另一基板处理系统180的示意性截面图。基板处理系统180类似于图1A的基板处理系统132，除了基板处理系统180被配置成使来自气体面板130的处理气体经由侧壁101跨基板190的顶表面191径向流动。此外，图1A中描绘的气体分配组件120由电极182替换。电极182可被配置成用于二次电子生成。在一个实施例中，电极182是含硅电极。
图2描绘在图1A和图1B的处理系统中使用的基板支撑组件146的示意性截面图，基板支撑组件146可用于实施本文所述的实施例。参考图2，静电吸盘150可包括加热元件170，加热元件170适合用于控制支撑在静电吸盘150的上表面192上的基板190的温度。加热元件170可以嵌入静电吸盘150中。可通过从加热器电源106将电流施加到加热器元件170来电阻式加热静电吸盘150。加热器电源106可通过RF滤波器216耦合，以保护加热器电源106免受RF能量的影响。从加热器电源106供应的电流由控制器110调控，以控制加热器元件170所生成的热量，由此在膜沉积期间将基板190和静电吸盘150保持在基本上恒定的温度。在基板上沉积类金刚石碳膜期间，可调整所供应的电流，以将静电吸盘150的温度选择性地控制在约-50℃至约350℃之间。
参考图1A和图1B，可将诸如热电偶之类的温度传感器172嵌入静电吸盘150中，以监测静电吸盘150的温度。所测量到的温度由控制器110使用以控制供应到加热器元件170的功率，以将基板保持在期望的温度。
返回参考图2，静电吸盘150包括吸附电极210，吸附电极210可以是导电材料的网格(mesh)。吸附电极210可嵌入静电吸盘150中。吸附电极210耦接至吸附电源212，吸附电源212在通电时将基板190静电夹持到静电吸盘150的上表面192。
吸附电极210可配置成单极或双极电极，或具有另一适合的布置。吸附电极210可以通过RF滤波器214耦接至吸附电源212，吸附电源212提供直流(DC)功率以将基板190静电固定到静电吸盘150的上表面192。RF滤波器214防止用于在工艺腔室100内形成等离子体的RF功率损坏电气设备。静电吸盘150可由诸如AlN或Al2O3之类的陶瓷材料制成。
功率应用系统220耦接至基板支撑组件146。功率应用系统220可包括加热器电源106、吸附电源212、第一射频(RF)电源230、以及第二RF电源240。功率应用系统220的实施例可以另外包括控制器110、以及传感器装置250，传感器装置250与控制器110以及第一RF电源230和第二RF电源240两者通信。控制器110也可用于通过应用来自第一RF电源230和第二RF电源240的RF功率来控制来自处理气体的等离子体，以便在基板190上沉积材料层。
如上文所述，静电吸盘150包括吸附电极210，吸附电极210在一方面可起到吸附基板190的作用，同时还用作第一RF电极。静电吸盘150也可包括第二RF电极260，并且与吸附电极210一起可施加RF功率以调谐等离子体。第一RF电源230可以耦接至第二RF电极260，而第二RF电源240可耦接至吸附电极210。可以分别为第一RF电源230和第二RF电源240提供第一匹配网络和第二匹配网络。第二RF电极260可以是导电材料的实心(solid)金属板或导电材料的网格。
第一RF电源230和第二RF电源240可以以相同频率或不同频率产生功率。在一些实施例中，第一RF电源230和第二RF电源240中的一者或两者可独立地以从约350KHz到约162MHz(例如，350KHz、2MHz、13.56MHz、27MHz、40MHz、60MHz、100MHz、或162MHz)的频率产生功率。可以改变来自第一RF电源230和第二RF电源240中的一者或两者的RF功率，以便调谐等离子体。
通常，关于图1A、图1B和图2描述的系统可以用于根据本文描述的实施例沉积碳膜。根据本文所述的实施例制造的碳膜(例如，一个或多个碳层)本质上是非晶的并且具有高的sp3碳含量(例如，类金刚石)。沉积态的(as-deposited)类金刚石碳层具有小于0.1(例如0.09)的消光系数或k值(K(在633nm处))、大于1.8g/cc(例如大约2.0g/cc或更高、大约2.5g/cc或更高、诸如从约1.8g/cc至约2.5g/cc)的密度(g/cc)、大于2.0(例如，大约2.0至大约3.0，诸如2.3)的折射率或n值(n(在633nm处))、小于约-100MPa(例如从约-1000MPa至约-100MPa，诸如约-550MPa)的应力(MPa)、以及约150GPa或更大(例如，从约200GPa至约400GPa)的弹性模量(GPa)。在本公开的各种实施例中，沉积态的类金刚石碳层可含有至少40％的sp3杂化碳原子或更多，诸如约60％或更多，例如约90％的sp3杂化碳原子。沉积态的类金刚石碳层的厚度可在约5埃至约20,000埃之间。
具有以上特性的类金刚石碳层可以使用下文的示例性沉积工艺参数形成。基板温度可在从约-50℃至约350℃(例如，从约-10℃至约20℃)的范围内。腔室压力可在从约0.5毫托到约10托(例如，约5毫托到约10毫托)的范围内。含碳氢化合物的气体混合物的流速可以是从约10sccm至约1,000sccm(例如，约100sccm至约200sccm)。稀释气体的流速可个别地在从约50sccm至约5000sccm(例如，从约50sccm至约200sccm)的范围内。下表I示出示例性的沉积工艺参数，在可从美国加利福尼亚州圣克拉拉市的应用材料公司购得的沉积腔室中的300mm基板上执行所述沉积工艺参数。
表I
Figure BDA0002982682580000071
图3描绘根据本发明的一个实施例的用于在设置在基板上的膜堆叠上形成类金刚石碳层的方法300的流程图。形成在膜堆叠上的类金刚石碳层可用于例如作为硬掩模，以在膜堆叠中形成阶梯状结构。图4A至图4B是示出根据方法300的用于在设置在基板上的膜堆叠上形成类金刚石碳层的序列。也应当理解，在图3中描绘的操作可同时执行和/或以与所描绘的顺序不同的顺序执行。
方法300在操作310处开始于将基板(诸如图4A中所描绘的基板400)定位至工艺腔室(诸如图1A或图1B中所描绘的工艺腔室100)中。基板400可以是图1A、图1B和图2中描绘的基板190。基板400可定位在静电吸盘上，例如，静电吸盘150的上表面192上。根据需要，基板400可以是以硅基材料或任何适合的绝缘材料、导电材料或半导体材料，具有设置在基板400上的膜堆叠404，膜堆叠404可用于在膜堆叠404中形成结构402(诸如阶梯状结构)。
如在图4A中描绘的示例性实施例所示，基板400可具有基本上平坦的表面、不平坦的表面、或上面形成有结构的基本上平坦的表面。膜堆叠404形成在基板400上。在一个实施例中，膜堆叠404可用于在前端或后端工艺中形成栅极结构、接触结构或互连结构。方法300可以在膜堆叠404上执行，以在膜堆叠404中形成用于在存储器结构中使用的阶梯状结构(诸如NAND结构)。在一个实施例中，基板400可以是诸如结晶硅(例如，Si<100>或Si<111>)、氧化硅、应变硅、硅锗、掺杂或未掺杂多晶硅、掺杂或未掺杂的硅基板和图案化或非图案化的基板的绝缘体上硅(SOI)、碳掺杂的氧化硅、氮化硅、掺杂硅、锗、砷化镓、玻璃、蓝宝石之类的材料。基板400可具有各种尺寸，诸如200mm、300mm、和450mm或其他直径的基板，以及矩形或正方形面板。除非另有说明，否则本文描述的实施例和示例是在具有200mm直径、300mm直径的基板、或450mm直径的基板上进行。在其中SOI结构用于基板400的实施例中，基板400可包括设置在硅结晶基板上的埋入介电层。在本文描绘的实施例中，基板400可以是结晶硅基板。
在一个实施例中，设置在基板400上的膜堆叠404可具有许多垂直堆叠的层。膜堆叠404可以包括在膜堆叠404中重复地形成的包括第一层(示出为408a1、408a2、408a3、……、408an)和第二层(示出为408b1、408b2、408b3、……、408bn)的多个对。重复地形成包括交替的第一层(示出为408a1、408a2、408a3、……、408an)和第二层(示出为408b1、408b2、408b3、……、408bn)的所述对，直到达到期望的第一层与第二层的对数为止。
膜堆叠404可以是半导体芯片(诸如三维存储器芯片)的一部分。尽管在图4A至图4B中示出了第一层(示出为408a1、408a2、408a3、……、408an)与第二层(示出为408b1、408b2、408b3、……、408bn)的三个重复层，但应注意，可根据需要使用第一层和第二层的任何期望数量的重复对。
在一个实施例中，膜堆叠404可以用于形成三维存储器芯片的多个栅极结构。形成在膜堆叠404中的第一层408a1、408a2、408a3、……、408an可以是第一介电层，并且第二层408b1、408b2、408b3、……、408bn可以是第二介电层。适合的介电层可用于形成第一层408a1、408a2、408a3、……、408an和第二层408b1、408b2、408b3、……、408bn，包括氧化硅、氮化硅、氮氧化硅、碳化硅、碳氧化硅、氮化钛、氧化物与氮化物的复合物、将氮化物层夹在中间的至少一个或多个氧化物层、以及它们的组合。在一些实施例中，介电层可以是介电常数大于4的高k材料。高k材料的适合示例包括二氧化铪(HfO2)、二氧化锆(ZrO2)、氧化硅铪(HfSiO2)、氧化铝铪(HfAlO)、氧化硅锆(ZrSiO2)、二氧化钽(TaO2)、氧化铝、掺杂铝的二氧化铪、铋锶钛(BST)、以及铂锆钛(PZT)等。
在一个特定示例中，第一层408a1、408a2、408a3、……、408an是氧化硅层，并且第二层408b1、408b2、408b3、……、408bn是设置在第一层408a1、408a2、408a3、……、408an上的氮化硅层或多晶硅层。在一个实施例中，第一层408a1、408a2、408a3、……、408an的厚度可被控制在约50埃与约1000埃之间(诸如约500埃)，并且每个第二层408b1、408b2、408b3、……、408bn的厚度可被控制在约50埃与约1000埃之间(诸如约500埃)。膜堆叠404的总厚度可在约100埃与约2000埃之间，并且可以随着技术的发展而变化。
注意，类金刚石碳层可在基板400上存在或不存在膜堆叠404的情况下形成在基板400的任何表面或任何部分上。
在操作320处，将吸附电压施加至静电吸盘，以将基板400夹持到静电吸盘。经由吸附电极210将电偏压提供给基板400。吸附电极210可以与吸附电源212电连通，吸附电源212供应偏压电压给吸附电极210。在一个实施例中，吸附电压在约10伏特和约3000伏特之间。
在操作320期间，处理空间中的工艺压力可保持在约0.1毫托至约10托(例如，约0.5毫托至约15毫托)，并且处理温度和/或基板温度可以保持在约-50℃至约350℃(例如约-10℃至约20℃)。
在操作330处，含碳氢化合物的气体混合物流入处理空间126。含碳氢化合物的气体混合物可通过气体分配组件120或经由侧壁101从气体面板130流入处理空间126。含碳氢化合物的气体混合物可包括至少一种碳氢化合物。含碳氢化合物的气体混合物可进一步包括惰性气体、稀释气体或它们的任何组合。在一些实施例中，在操作330期间保持在操作320期间供应的吸附电压。在一些实施例中，在操作320期间建立的工艺条件在操作330期间被保持。
在一个实施例中，碳氢化合物是气态碳氢化合物。在一个实施例中，碳氢化合物具有通式CxHy，其中x的范围在1至20之间，并且y的范围在1至20之间。适合的碳氢化合物包括例如C2H2、C3H6、CH4、C4H8、1,3-二甲基金刚烷、双环[2.2.1]庚-2,5-二烯(2,5-降冰片二烯)、金刚烷(C10H16)、降冰片烯(C7H10)或它们的组合。
一些实施例中，含碳氢化合物的气体混合物进一步包含一种或多种稀释气体。适合的稀释气体可包括但不限于氦气(He)、氩气(Ar)、氙气(Xe)、氢气(H2)、氮气(N2)、氨气(NH3)或它们的任何组合。在一个实施例中，稀释气体包括Ar、He和N2的组合。在一个实施例中，稀释气体包括Ar、He和H2的组合。
在一些实施例中，含碳氢化合物的气体混合物进一步包含惰性气体。在一些实施例中，可以将惰性气体(诸如氩气(Ar)和/或氦气(He))与含碳氢化合物的气体混合物一起供应到处理空间126中。其他惰性气体(诸如氮气(N2)和一氧化氮(NO))也可用于控制类金刚石碳层的密度和沉积速率。
在操作340处，如图4B所示，在基板水平处生成等离子体以在膜堆叠上形成类金刚石碳膜。可以通过向静电吸盘施加第一RF偏压来生成等离子体。第一RF偏压可以是从约10瓦至约3000瓦，在从约350KHz到大约162MHz(例如，350KHz、2MHz、13.56MHz、27MHz、40MHz、60MHz、100MHz、或162MHz)的频率。在一个实施例中，以在约1500瓦至约2500瓦之间(例如，1800-2200瓦)的功率以及约40MHz或更高的频率来提供第一RF偏压。在一个实施例中，第一RF偏压经由第二RF电极260提供给静电吸盘150。第二RF电极260可与供应偏压电压给第二RF电极260的第一RF电源230电连通。第一RF电源230可以以从约350KHz到约100MHz(例如，350KHz、2MHz、13.56MHz、27MHz、40MHz、60MHz或100MHz)的频率产生功率。
在一些实施例中，操作340进一步包括将第二RF偏压施加到静电吸盘以独立地控制离子密度和离子能量以调节膜应力。第二RF偏压可以是从约10瓦至约3000瓦，并且在约350KHz至约100MHz(例如，350KHz、2MHz、13.56MHz、27MHz、40MHz、60MHz或100MHz)的频率。在一个实施例中，以约800瓦和约1200瓦之间的功率以及约13.56MHz或更低的频率(例如约2MHz)来提供第二RF偏压。在一个实施例中，经由吸附电极210将第二RF偏压提供给基板400。吸附电极210可与供应偏压电压给吸附电极210的第二RF电源240电连通。以在约10瓦和约3000瓦之间的功率提供第二RF偏压。在一个实施例中，以在约800瓦和约1200瓦之间的功率提供第二RF偏压。在一个实施例中，在操作340期间保持在操作320中供应的吸附电压。
在可与本公开的任何其他实施例组合的一些实施例中，在操作340期间，第一RF偏压经由吸附电极210提供至基板400，并且第二RF偏压可经由第二RF电极260提供至基板400。
在可与本公开的任何其他实施例组合的一些实施例中，在操作340期间，将第一RF偏压提供给气体分配组件120或电极182，并且可经由第二RF电极260或吸附电极210将第二RF偏压提供至基板400。在这种情况下，施加到气体分配组件120或电极182的第一RF偏压可具有高频率，并且施加到第二RF电极260或吸附电极210的第二RF偏压可具有低频率。
第一RF偏压和第二RF偏压可使用功率电平和频率的各种组合。在一些实施例中，第一RF偏压可在约40MHz、60MHz或162MHz处为约2000瓦，并且第二RF偏压可在350KHz处为约1000瓦。在一些实施例中，第一RF偏压可在40MHz、60MHz或162MHz处为约2000瓦，并且第二RF偏压可在2MHz处为约1000瓦。在一些实施例中，第一RF偏压可在约40MHz、60MHz、或162MHz处为约2000瓦，并且第二RF偏压可在13.56MHz处为约1000瓦。
在可以与本公开的任何其他实施例组合的一些另外的实施例中，在操作340期间，第一RF偏压经由吸附电极210提供给基板400，第二RF偏压可经由第二RF电极260提供给基板400，并且第三RF偏压可提供至气体分配组件120或电极182。在这种情况下，第一RF偏压和第二RF偏压可以是本公开中所讨论的频率和功率的任意组合，并且第三RF偏压可以被配置成具有与本文讨论的第一RF偏压或第二RF偏压的功率和频率相同的功率和频率。
在一些实施例中，在操作340期间在基板上形成类金刚石碳层412之后，将类金刚石碳层412暴露于氢自由基。在一些实施例中，类金刚石碳层在操作340的沉积工艺期间暴露于氢自由基。在一些实施例中，氢自由基在RPS中形成并且被输送至处理区域。不受理论的束缚，但据信，将类金刚石碳层暴露于氢自由基会导致对sp2杂化碳原子的选择性蚀刻，从而增加了膜的sp3杂化碳原子的比例，从而提高了蚀刻选择性。
在操作350处，在基板上形成类钻石碳层412之后，将基板解吸附。在操作350期间，关闭吸附电压。关闭反应性气体，并且可选地从处理腔室中清除反应性气体。在一个实施例中，在操作350期间，减少RF功率(例如，约200W)。一旦基板从静电吸盘解吸附，就将剩余的气体从处理腔室中清除。将处理腔室抽空降压，并且将基板在升降杆上向上移动，然后从工艺腔室移出。
在基板上形成类金刚石碳层412之后，可以在蚀刻工艺中将类金刚石碳层412用作图案化掩模以形成三维结构(诸如阶梯状结构)。可以使用标准的光致抗蚀剂图案化技术将类金刚石碳层412图案化。
提供下文的非限制性示例以进一步说明本文所述的实施例。然而，示例并非旨在全部涵盖，也不旨在限制本文所述实施例的范围。在一个实施例中，本公开的低应力、高密度类金刚石碳膜是通过下述方式制造：使作为工艺气体的150sccm的C2H2和100sccm的He在10℃的温度流动，在具有Ar和/或He作为稀释气体的CVD反应器中，施加2000瓦的RF(60MHz)功率通过基板基座(静电吸盘)。下表II中示出所得的类金刚石碳膜、非晶碳参考膜以及通过PVD形成的类金刚石碳膜之间的比较。
表II
Figure BDA0002982682580000131
因此，提供了用于形成高透明度的类金刚石碳硬掩模层的方法和设备，所述类金刚石碳硬掩模层可用于形成阶梯状结构，以用于制造半导体器件的三维堆叠。通过利用具有期望的稳健膜性质和蚀刻选择性的类金刚石硬掩模层，可获得在膜堆叠中形成的所得结构的改善的尺寸和轮廓(profile)控制，并且可以在半导体器件的三维堆叠的应用中增强芯片器件的电性能。
尽管前述内容是针对本公开的实施例，但是在不脱离本公开的基本范围的情况下，可以设计本公开的其他和进一步的实施例，并且本公开的范围由所附权利要求确定。

Claims (15)

1.一种在基板上形成碳膜的方法，包括：
使含碳氢化合物的气体混合物流入具有定位在静电吸盘上的基板的工艺腔室中，其中所述基板保持在约-10℃至约20℃的温度和约0.5毫托至约10托的腔室压力；以及
通过将第一RF偏压施加至所述静电吸盘来生成等离子体，以在所述基板上沉积含有约60％或更多的杂化sp3原子的类金刚石碳膜，其中所述第一RF偏压是以约1800瓦至约2200瓦的功率和约40MHz至约162MHz的频率提供。
2.如权利要求1所述的方法，其中生成等离子体进一步包括：将第二RF偏压施加至所述静电吸盘。
3.如权利要求2所述的方法，其中所述第二RF偏压是以约800瓦至约1200瓦的功率和约350KHz至约13.56MHz的频率提供。
4.如权利要求2所述的方法，其中所述第一RF偏压是以约2000瓦的功率和约60MHz的频率提供，并且所述第二RF偏压是以约1000瓦的功率和约2MHz的频率提供。
5.如权利要求1所述的方法，其中所述基板保持在约10℃的温度。
6.一种在基板上形成碳膜的方法，包括：
使含碳氢化合物的气体混合物流入具有定位在静电吸盘上的基板的工艺腔室中；以及
通过将第一RF偏压施加至所述静电吸盘以及将第二RF偏压施加至设置在所述静电吸盘上方且相对的电极来生成等离子体，以在所述基板上沉积类金刚石碳膜，
其中所述第一RF偏压是以约13.56MHz或更低的频率提供，并且所述第二RF偏压是以约40MHz或更高的频率提供，并且所述基板保持在约-10℃至约20℃的温度和约0.5毫托至约10托的腔室压力。
7.如权利要求6所述的方法，其中所述第一RF偏压是以约2MHz的频率和约800瓦至约1200瓦的功率提供。
8.如权利要求6所述的方法，其中所述第二RF偏压是以约60MHz的频率和约1500瓦至约2500瓦的功率提供。
9.如权利要求6所述的方法，其中生成等离子体进一步包括：将第三RF偏压施加至设置在所述静电吸盘上方且相对的电极。
10.如权利要求6所述的方法，其中所述第三RF偏压是以约10瓦至约3000瓦的功率和从约350KHz至约162MHz的频率提供。
11.一种处理基板的方法，包括：
使含碳氢化合物的气体混合物流入具有定位在静电吸盘上的基板的工艺腔室的处理空间中，其中所述基板保持在约5毫托之间的压力，并且其中所述含碳氢化合物的气体混合物包括乙炔(C2H2)；
通过将第一RF偏压施加至所述静电吸盘来在所述基板水平(level)处生成等离子体，以在所述基板上沉积类金刚石碳膜，其中所述第一RF偏压是以约2000瓦的功率和约60MHz的频率提供；
在所述类金刚石碳膜之上形成图案化的光致抗蚀剂层；
以对应于所图案化的光致抗蚀剂层的图案来蚀刻所述类金刚石碳膜；以及
将材料沉积至所述类金刚石碳膜的所蚀刻的部分中。
12.如权利要求11所述的方法，其中生成等离子体进一步包括：将第二RF偏压施加至所述静电吸盘，其中所述第二RF偏压是以约1000瓦的功率和约2MHz的频率提供。
13.如权利要求11所述的方法，其中所述类金刚石碳膜用作远紫外(“EUV”)光刻工艺中的下层(underlayer)。
14.如权利要求11所述的方法，其中所述含碳氢化合物的气体混合物进一步包括稀释气体，所述稀释气体包括：He、Ar、Xe、N2、H2、或它们的任何组合。
15.如权利要求14所述的方法，其中所述含碳氢化合物的气体混合物通过设置在所述工艺腔室的侧壁处的气体面板流入所述工艺腔室中。
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