JP7110204B2 - イントリンシックゲッタリングおよびゲート酸化物完全性歩留まりを有するシリコンウエハを処理する方法 - Google Patents
イントリンシックゲッタリングおよびゲート酸化物完全性歩留まりを有するシリコンウエハを処理する方法 Download PDFInfo
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- JP7110204B2 JP7110204B2 JP2019535384A JP2019535384A JP7110204B2 JP 7110204 B2 JP7110204 B2 JP 7110204B2 JP 2019535384 A JP2019535384 A JP 2019535384A JP 2019535384 A JP2019535384 A JP 2019535384A JP 7110204 B2 JP7110204 B2 JP 7110204B2
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- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/324—Thermal treatment for modifying the properties of semiconductor bodies, e.g. annealing, sintering
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- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/322—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to modify their internal properties, e.g. to produce internal imperfections
- H01L21/3221—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to modify their internal properties, e.g. to produce internal imperfections of silicon bodies, e.g. for gettering
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- C30B33/00—After-treatment of single crystals or homogeneous polycrystalline material with defined structure
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- C30B33/00—After-treatment of single crystals or homogeneous polycrystalline material with defined structure
- C30B33/005—Oxydation
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- C30B33/00—After-treatment of single crystals or homogeneous polycrystalline material with defined structure
- C30B33/02—Heat treatment
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- C30B—SINGLE-CRYSTAL GROWTH; UNIDIRECTIONAL SOLIDIFICATION OF EUTECTIC MATERIAL OR UNIDIRECTIONAL DEMIXING OF EUTECTOID MATERIAL; REFINING BY ZONE-MELTING OF MATERIAL; PRODUCTION OF A HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; SINGLE CRYSTALS OR HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; AFTER-TREATMENT OF SINGLE CRYSTALS OR A HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; APPARATUS THEREFOR
- C30B33/00—After-treatment of single crystals or homogeneous polycrystalline material with defined structure
- C30B33/08—Etching
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- H01L21/02104—Forming layers
- H01L21/02365—Forming inorganic semiconducting materials on a substrate
- H01L21/02518—Deposited layers
- H01L21/02587—Structure
- H01L21/0259—Microstructure
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- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
- H01L21/304—Mechanical treatment, e.g. grinding, polishing, cutting
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- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/322—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to modify their internal properties, e.g. to produce internal imperfections
- H01L21/3221—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to modify their internal properties, e.g. to produce internal imperfections of silicon bodies, e.g. for gettering
- H01L21/3225—Thermally inducing defects using oxygen present in the silicon body for intrinsic gettering
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- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
- H10D62/60—Impurity distributions or concentrations
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- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
- H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
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- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
- H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
- H01L21/3065—Plasma etching; Reactive-ion etching
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Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2022115481A JP7541551B2 (ja) | 2016-12-28 | 2022-07-20 | イントリンシックゲッタリングおよびゲート酸化物完全性歩留まりを有するシリコンウエハを処理する方法 |
Applications Claiming Priority (3)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US201662439621P | 2016-12-28 | 2016-12-28 | |
| US62/439,621 | 2016-12-28 | ||
| PCT/US2017/066063 WO2018125565A1 (en) | 2016-12-28 | 2017-12-13 | Method of treating silicon wafers to have intrinsic gettering and gate oxide integrity yield |
Related Child Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2022115481A Division JP7541551B2 (ja) | 2016-12-28 | 2022-07-20 | イントリンシックゲッタリングおよびゲート酸化物完全性歩留まりを有するシリコンウエハを処理する方法 |
Publications (3)
| Publication Number | Publication Date |
|---|---|
| JP2020504069A JP2020504069A (ja) | 2020-02-06 |
| JP2020504069A5 JP2020504069A5 (enExample) | 2021-01-28 |
| JP7110204B2 true JP7110204B2 (ja) | 2022-08-01 |
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| Application Number | Title | Priority Date | Filing Date |
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| JP2019535384A Active JP7110204B2 (ja) | 2016-12-28 | 2017-12-13 | イントリンシックゲッタリングおよびゲート酸化物完全性歩留まりを有するシリコンウエハを処理する方法 |
| JP2022115481A Active JP7541551B2 (ja) | 2016-12-28 | 2022-07-20 | イントリンシックゲッタリングおよびゲート酸化物完全性歩留まりを有するシリコンウエハを処理する方法 |
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| Application Number | Title | Priority Date | Filing Date |
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| JP2022115481A Active JP7541551B2 (ja) | 2016-12-28 | 2022-07-20 | イントリンシックゲッタリングおよびゲート酸化物完全性歩留まりを有するシリコンウエハを処理する方法 |
Country Status (8)
| Country | Link |
|---|---|
| US (2) | US10453703B2 (enExample) |
| EP (2) | EP3562978B1 (enExample) |
| JP (2) | JP7110204B2 (enExample) |
| KR (2) | KR102306730B1 (enExample) |
| CN (2) | CN110799678B (enExample) |
| SG (1) | SG10201913071XA (enExample) |
| TW (2) | TWI724266B (enExample) |
| WO (1) | WO2018125565A1 (enExample) |
Families Citing this family (16)
| Publication number | Priority date | Publication date | Assignee | Title |
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| JP6447439B2 (ja) * | 2015-09-28 | 2019-01-09 | 信越半導体株式会社 | 貼り合わせsoiウェーハの製造方法 |
| KR102306730B1 (ko) * | 2016-12-28 | 2021-09-30 | 썬에디슨 세미컨덕터 리미티드 | 고유 게터링 및 게이트 산화물 무결성 수율을 갖도록 규소 웨이퍼들을 처리하는 방법 |
| DE102017219255A1 (de) * | 2017-10-26 | 2019-05-02 | Siltronic Ag | Halbleiterscheibe aus einkristallinem Silizium |
| CN108961218B (zh) * | 2018-06-11 | 2021-07-02 | 无锡维胜威信息科技有限公司 | 太阳能硅片晶花提取方法 |
| US10943813B2 (en) * | 2018-07-13 | 2021-03-09 | Globalwafers Co., Ltd. | Radio frequency silicon on insulator wafer platform with superior performance, stability, and manufacturability |
| JP7388434B2 (ja) * | 2019-04-16 | 2023-11-29 | 信越半導体株式会社 | シリコン単結晶ウェーハの製造方法及びシリコン単結晶ウェーハ |
| JP7251616B2 (ja) * | 2019-04-26 | 2023-04-04 | 富士電機株式会社 | 半導体装置および製造方法 |
| CN114631193A (zh) * | 2019-08-09 | 2022-06-14 | 尖端设备技术公司 | 具有低氧浓度区域的晶片 |
| US11742203B2 (en) * | 2020-02-26 | 2023-08-29 | The Hong Kong University Of Science And Technology | Method for growing III-V compound semiconductor thin films on silicon-on-insulators |
| US11695048B2 (en) * | 2020-04-09 | 2023-07-04 | Sumco Corporation | Silicon wafer and manufacturing method of the same |
| TWI768957B (zh) * | 2021-06-08 | 2022-06-21 | 合晶科技股份有限公司 | 複合基板及其製造方法 |
| CN113793800B (zh) * | 2021-08-18 | 2024-04-09 | 万华化学集团电子材料有限公司 | 一种半导体单晶硅片的除杂工艺及制造工艺 |
| TWI865954B (zh) * | 2021-11-04 | 2024-12-11 | 日商Sumco股份有限公司 | 矽晶圓及磊晶矽晶圓 |
| JP7658332B2 (ja) * | 2021-11-04 | 2025-04-08 | 株式会社Sumco | シリコンウェーハおよびエピタキシャルシリコンウェーハ |
| TWI854344B (zh) * | 2021-11-04 | 2024-09-01 | 日商Sumco股份有限公司 | 矽晶圓及磊晶矽晶圓 |
| CN116259538B (zh) * | 2023-03-30 | 2023-11-17 | 苏州龙驰半导体科技有限公司 | 提高SiC材料栅氧界面态质量的方法及其应用 |
Citations (1)
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| JP2016015426A (ja) | 2014-07-03 | 2016-01-28 | 信越半導体株式会社 | シリコン単結晶ウェーハの熱処理方法 |
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Also Published As
| Publication number | Publication date |
|---|---|
| CN110799678B (zh) | 2021-11-26 |
| CN114093764A (zh) | 2022-02-25 |
| SG10201913071XA (en) | 2020-03-30 |
| KR20210122867A (ko) | 2021-10-12 |
| TW201840920A (zh) | 2018-11-16 |
| KR102453743B1 (ko) | 2022-10-11 |
| KR102306730B1 (ko) | 2021-09-30 |
| US10453703B2 (en) | 2019-10-22 |
| EP3653761A1 (en) | 2020-05-20 |
| CN114093764B (zh) | 2025-07-22 |
| WO2018125565A1 (en) | 2018-07-05 |
| US20190267251A1 (en) | 2019-08-29 |
| JP2022169511A (ja) | 2022-11-09 |
| TW202129094A (zh) | 2021-08-01 |
| CN110799678A (zh) | 2020-02-14 |
| JP7541551B2 (ja) | 2024-08-28 |
| EP3562978A1 (en) | 2019-11-06 |
| EP3562978B1 (en) | 2021-03-10 |
| JP2020504069A (ja) | 2020-02-06 |
| KR20190101414A (ko) | 2019-08-30 |
| US20180182641A1 (en) | 2018-06-28 |
| EP3653761B1 (en) | 2024-02-28 |
| TWI764661B (zh) | 2022-05-11 |
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