JP7068957B2 - 配線基板、半導体装置及び配線基板の製造方法 - Google Patents

配線基板、半導体装置及び配線基板の製造方法 Download PDF

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Publication number
JP7068957B2
JP7068957B2 JP2018143361A JP2018143361A JP7068957B2 JP 7068957 B2 JP7068957 B2 JP 7068957B2 JP 2018143361 A JP2018143361 A JP 2018143361A JP 2018143361 A JP2018143361 A JP 2018143361A JP 7068957 B2 JP7068957 B2 JP 7068957B2
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Japan
Prior art keywords
layer
opening
wiring
base plating
plating layer
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JP2018143361A
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English (en)
Japanese (ja)
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JP2020021796A5 (https=
JP2020021796A (ja
Inventor
貴志 荒井
史雅 片桐
克哉 深瀬
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Shinko Electric Industries Co Ltd
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Shinko Electric Industries Co Ltd
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Publication date
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Priority to JP2018143361A priority Critical patent/JP7068957B2/ja
Priority to US16/523,573 priority patent/US10892217B2/en
Publication of JP2020021796A publication Critical patent/JP2020021796A/ja
Publication of JP2020021796A5 publication Critical patent/JP2020021796A5/ja
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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/01—Manufacture or treatment
    • H10W70/05—Manufacture or treatment of insulating or insulated package substrates, or of interposers, or of redistribution layers
    • H10W70/093—Connecting or disconnecting other interconnections thereto or therefrom, e.g. connecting bond wires or bumps
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/60—Insulating or insulated package substrates; Interposers; Redistribution layers
    • H10W70/62—Insulating or insulated package substrates; Interposers; Redistribution layers characterised by their interconnections
    • H10W70/65—Shapes or dispositions of interconnections
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/01—Manufacture or treatment
    • H10W70/05—Manufacture or treatment of insulating or insulated package substrates, or of interposers, or of redistribution layers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/60—Insulating or insulated package substrates; Interposers; Redistribution layers
    • H10W70/67—Insulating or insulated package substrates; Interposers; Redistribution layers characterised by their insulating layers or insulating parts
    • H10W70/68—Shapes or dispositions thereof
    • H10W70/685—Shapes or dispositions thereof comprising multiple insulating layers
    • H10W70/687—Shapes or dispositions thereof comprising multiple insulating layers characterized by the outer layers being for protection, e.g. solder masks, or for protection against chemical or mechanical damage
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W99/00—Subject matter not provided for in other groups of this subclass
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H10W90/721—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bump connectors
    • H10W90/724—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bump connectors between a chip and a stacked insulating package substrate, interposer or RDL

Landscapes

  • Engineering & Computer Science (AREA)
  • Ceramic Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Geometry (AREA)
  • Production Of Multi-Layered Print Wiring Board (AREA)
  • Printing Elements For Providing Electric Connections Between Printed Circuits (AREA)
  • Electric Connection Of Electric Components To Printed Circuits (AREA)
JP2018143361A 2018-07-31 2018-07-31 配線基板、半導体装置及び配線基板の製造方法 Active JP7068957B2 (ja)

Priority Applications (2)

Application Number Priority Date Filing Date Title
JP2018143361A JP7068957B2 (ja) 2018-07-31 2018-07-31 配線基板、半導体装置及び配線基板の製造方法
US16/523,573 US10892217B2 (en) 2018-07-31 2019-07-26 Wiring substrate and semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2018143361A JP7068957B2 (ja) 2018-07-31 2018-07-31 配線基板、半導体装置及び配線基板の製造方法

Publications (3)

Publication Number Publication Date
JP2020021796A JP2020021796A (ja) 2020-02-06
JP2020021796A5 JP2020021796A5 (https=) 2021-07-29
JP7068957B2 true JP7068957B2 (ja) 2022-05-17

Family

ID=69228999

Family Applications (1)

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JP2018143361A Active JP7068957B2 (ja) 2018-07-31 2018-07-31 配線基板、半導体装置及び配線基板の製造方法

Country Status (2)

Country Link
US (1) US10892217B2 (https=)
JP (1) JP7068957B2 (https=)

Families Citing this family (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2021093417A (ja) * 2019-12-09 2021-06-17 イビデン株式会社 プリント配線板、及び、プリント配線板の製造方法
US10741483B1 (en) 2020-01-28 2020-08-11 Advanced Semiconductor Engineering, Inc. Substrate structure and method for manufacturing the same
CN112002752B (zh) * 2020-07-27 2023-04-21 北海惠科光电技术有限公司 源漏电极的制备方法、阵列基板的制备方法和显示机构
JP7638812B2 (ja) * 2021-07-19 2025-03-04 新光電気工業株式会社 配線基板及び配線基板の製造方法
KR20230030995A (ko) * 2021-08-26 2023-03-07 엘지이노텍 주식회사 회로 기판 및 이를 포함하는 패키지 기판
KR20240059139A (ko) * 2022-10-27 2024-05-07 삼성전기주식회사 인쇄회로기판
US20240304461A1 (en) * 2023-03-07 2024-09-12 Tong Hsing Electronic Industries, Ltd. Ceramic submount for semiconductor device and method for manufacturing the same

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2005191131A (ja) 2003-12-24 2005-07-14 Ngk Spark Plug Co Ltd 配線基板の製造方法
US20070007665A1 (en) 2005-07-05 2007-01-11 Interantional Business Machines Corporation Structure and method for producing multiple size interconnections
JP2008227355A (ja) 2007-03-15 2008-09-25 Shinko Electric Ind Co Ltd 電子装置及びその製造方法
JP2013229523A (ja) 2012-04-26 2013-11-07 Shinko Electric Ind Co Ltd パッド形成方法及び配線基板

Family Cites Families (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8614143B2 (en) * 2008-12-03 2013-12-24 Texas Instruments Incorporated Simultaneous via and trench patterning using different etch rates
KR101278426B1 (ko) 2010-09-02 2013-06-24 삼성전기주식회사 반도체 패키지 기판의 제조방법
US9245834B2 (en) * 2012-03-16 2016-01-26 Stats Chippac, Ltd. Semiconductor device and method of forming compliant conductive interconnect structure in flipchip package
JP2016051747A (ja) * 2014-08-29 2016-04-11 京セラサーキットソリューションズ株式会社 配線基板

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2005191131A (ja) 2003-12-24 2005-07-14 Ngk Spark Plug Co Ltd 配線基板の製造方法
US20070007665A1 (en) 2005-07-05 2007-01-11 Interantional Business Machines Corporation Structure and method for producing multiple size interconnections
JP2008227355A (ja) 2007-03-15 2008-09-25 Shinko Electric Ind Co Ltd 電子装置及びその製造方法
JP2013229523A (ja) 2012-04-26 2013-11-07 Shinko Electric Ind Co Ltd パッド形成方法及び配線基板

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US10892217B2 (en) 2021-01-12
US20200043841A1 (en) 2020-02-06
JP2020021796A (ja) 2020-02-06

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