JP7068957B2 - 配線基板、半導体装置及び配線基板の製造方法 - Google Patents

配線基板、半導体装置及び配線基板の製造方法 Download PDF

Info

Publication number
JP7068957B2
JP7068957B2 JP2018143361A JP2018143361A JP7068957B2 JP 7068957 B2 JP7068957 B2 JP 7068957B2 JP 2018143361 A JP2018143361 A JP 2018143361A JP 2018143361 A JP2018143361 A JP 2018143361A JP 7068957 B2 JP7068957 B2 JP 7068957B2
Authority
JP
Japan
Prior art keywords
layer
opening
wiring
base plating
plating layer
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Active
Application number
JP2018143361A
Other languages
English (en)
Japanese (ja)
Other versions
JP2020021796A (ja
JP2020021796A5 (enExample
Inventor
貴志 荒井
史雅 片桐
克哉 深瀬
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Shinko Electric Industries Co Ltd
Original Assignee
Shinko Electric Industries Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Shinko Electric Industries Co Ltd filed Critical Shinko Electric Industries Co Ltd
Priority to JP2018143361A priority Critical patent/JP7068957B2/ja
Priority to US16/523,573 priority patent/US10892217B2/en
Publication of JP2020021796A publication Critical patent/JP2020021796A/ja
Publication of JP2020021796A5 publication Critical patent/JP2020021796A5/ja
Application granted granted Critical
Publication of JP7068957B2 publication Critical patent/JP7068957B2/ja
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the groups H01L21/18 - H01L21/326 or H10D48/04 - H10D48/07
    • H01L21/4814—Conductive parts
    • H01L21/4846—Leads on or in insulating or insulated substrates, e.g. metallisation
    • H01L21/4853—Connection or disconnection of other leads to or from a metallisation, e.g. pins, wires, bumps
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49838—Geometry or layout
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the groups H01L21/18 - H01L21/326 or H10D48/04 - H10D48/07
    • H01L21/4803—Insulating or insulated parts, e.g. mountings, containers, diamond heatsinks
    • H01L21/481—Insulating layers on insulating parts, with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the groups H01L21/18 - H01L21/326 or H10D48/04 - H10D48/07
    • H01L21/4814—Conductive parts
    • H01L21/4846—Leads on or in insulating or insulated substrates, e.g. metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49811—Additional leads joined to the metallisation on the insulating substrate, e.g. pins, bumps, wires, flat leads
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Power Engineering (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Manufacturing & Machinery (AREA)
  • Ceramic Engineering (AREA)
  • Geometry (AREA)
  • Production Of Multi-Layered Print Wiring Board (AREA)
  • Printing Elements For Providing Electric Connections Between Printed Circuits (AREA)
  • Electric Connection Of Electric Components To Printed Circuits (AREA)
JP2018143361A 2018-07-31 2018-07-31 配線基板、半導体装置及び配線基板の製造方法 Active JP7068957B2 (ja)

Priority Applications (2)

Application Number Priority Date Filing Date Title
JP2018143361A JP7068957B2 (ja) 2018-07-31 2018-07-31 配線基板、半導体装置及び配線基板の製造方法
US16/523,573 US10892217B2 (en) 2018-07-31 2019-07-26 Wiring substrate and semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2018143361A JP7068957B2 (ja) 2018-07-31 2018-07-31 配線基板、半導体装置及び配線基板の製造方法

Publications (3)

Publication Number Publication Date
JP2020021796A JP2020021796A (ja) 2020-02-06
JP2020021796A5 JP2020021796A5 (enExample) 2021-07-29
JP7068957B2 true JP7068957B2 (ja) 2022-05-17

Family

ID=69228999

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2018143361A Active JP7068957B2 (ja) 2018-07-31 2018-07-31 配線基板、半導体装置及び配線基板の製造方法

Country Status (2)

Country Link
US (1) US10892217B2 (enExample)
JP (1) JP7068957B2 (enExample)

Families Citing this family (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2021093417A (ja) * 2019-12-09 2021-06-17 イビデン株式会社 プリント配線板、及び、プリント配線板の製造方法
US10741483B1 (en) * 2020-01-28 2020-08-11 Advanced Semiconductor Engineering, Inc. Substrate structure and method for manufacturing the same
CN112002752B (zh) 2020-07-27 2023-04-21 北海惠科光电技术有限公司 源漏电极的制备方法、阵列基板的制备方法和显示机构
JP7638812B2 (ja) * 2021-07-19 2025-03-04 新光電気工業株式会社 配線基板及び配線基板の製造方法
KR20230030995A (ko) * 2021-08-26 2023-03-07 엘지이노텍 주식회사 회로 기판 및 이를 포함하는 패키지 기판
KR20240059139A (ko) * 2022-10-27 2024-05-07 삼성전기주식회사 인쇄회로기판

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2005191131A (ja) 2003-12-24 2005-07-14 Ngk Spark Plug Co Ltd 配線基板の製造方法
US20070007665A1 (en) 2005-07-05 2007-01-11 Interantional Business Machines Corporation Structure and method for producing multiple size interconnections
JP2008227355A (ja) 2007-03-15 2008-09-25 Shinko Electric Ind Co Ltd 電子装置及びその製造方法
JP2013229523A (ja) 2012-04-26 2013-11-07 Shinko Electric Ind Co Ltd パッド形成方法及び配線基板

Family Cites Families (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8614143B2 (en) * 2008-12-03 2013-12-24 Texas Instruments Incorporated Simultaneous via and trench patterning using different etch rates
KR101278426B1 (ko) 2010-09-02 2013-06-24 삼성전기주식회사 반도체 패키지 기판의 제조방법
US9245834B2 (en) * 2012-03-16 2016-01-26 Stats Chippac, Ltd. Semiconductor device and method of forming compliant conductive interconnect structure in flipchip package
JP2016051747A (ja) * 2014-08-29 2016-04-11 京セラサーキットソリューションズ株式会社 配線基板

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2005191131A (ja) 2003-12-24 2005-07-14 Ngk Spark Plug Co Ltd 配線基板の製造方法
US20070007665A1 (en) 2005-07-05 2007-01-11 Interantional Business Machines Corporation Structure and method for producing multiple size interconnections
JP2008227355A (ja) 2007-03-15 2008-09-25 Shinko Electric Ind Co Ltd 電子装置及びその製造方法
JP2013229523A (ja) 2012-04-26 2013-11-07 Shinko Electric Ind Co Ltd パッド形成方法及び配線基板

Also Published As

Publication number Publication date
US20200043841A1 (en) 2020-02-06
US10892217B2 (en) 2021-01-12
JP2020021796A (ja) 2020-02-06

Similar Documents

Publication Publication Date Title
JP7068957B2 (ja) 配線基板、半導体装置及び配線基板の製造方法
JP6266907B2 (ja) 配線基板及び配線基板の製造方法
JP6247032B2 (ja) 配線基板、半導体装置及び配線基板の製造方法
JP7202784B2 (ja) 配線基板、半導体装置及び配線基板の製造方法
US9119319B2 (en) Wiring board, semiconductor device, and method for manufacturing wiring board
JP6228785B2 (ja) 配線基板、半導体装置及び配線基板の製造方法
US20150092356A1 (en) Printed wiring board, method for manufacturing printed wiring board and package-on-package
JP6608108B2 (ja) 配線基板、半導体装置及び配線基板の製造方法
TWI543676B (zh) 印刷電路板及其製造方法
US20150092357A1 (en) Printed wiring board, method for manufacturing printed wiring board and package-on-package
JP2007173775A (ja) 回路基板構造及びその製法
JP2017098306A (ja) 配線基板、半導体装置及び配線基板の製造方法
JP2018107349A (ja) 配線基板、配線基板の製造方法
JP6182309B2 (ja) 配線基板、半導体装置及び配線基板の製造方法
JP2021174871A (ja) 端子構造、配線基板及び端子構造の製造方法
JP5762376B2 (ja) 配線基板及びその製造方法
JP4769056B2 (ja) 配線基板及びその製法方法
KR20200106247A (ko) 버티컬 타입의 패시브 소자를 갖는 멀티 인쇄회로기판 및 그 제조 방법
KR102521788B1 (ko) 딥 캐비티 구조의 다층 인쇄회로기판 제조 방법
JP7430481B2 (ja) 配線基板、半導体装置及び配線基板の製造方法
JP7198154B2 (ja) 配線基板、及び配線基板の製造方法
JP6368635B2 (ja) 配線基板、半導体装置及び配線基板の製造方法
JP2025003669A (ja) 端子構造の製造方法
JP7532208B2 (ja) 配線基板、半導体装置及び配線基板の製造方法
KR102881013B1 (ko) 인쇄회로기판

Legal Events

Date Code Title Description
A521 Request for written amendment filed

Free format text: JAPANESE INTERMEDIATE CODE: A523

Effective date: 20210615

A621 Written request for application examination

Free format text: JAPANESE INTERMEDIATE CODE: A621

Effective date: 20210615

TRDD Decision of grant or rejection written
A977 Report on retrieval

Free format text: JAPANESE INTERMEDIATE CODE: A971007

Effective date: 20220330

A01 Written decision to grant a patent or to grant a registration (utility model)

Free format text: JAPANESE INTERMEDIATE CODE: A01

Effective date: 20220405

A61 First payment of annual fees (during grant procedure)

Free format text: JAPANESE INTERMEDIATE CODE: A61

Effective date: 20220502

R150 Certificate of patent or registration of utility model

Ref document number: 7068957

Country of ref document: JP

Free format text: JAPANESE INTERMEDIATE CODE: R150