JP2020021796A5 - - Google Patents
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- JP2020021796A5 JP2020021796A5 JP2018143361A JP2018143361A JP2020021796A5 JP 2020021796 A5 JP2020021796 A5 JP 2020021796A5 JP 2018143361 A JP2018143361 A JP 2018143361A JP 2018143361 A JP2018143361 A JP 2018143361A JP 2020021796 A5 JP2020021796 A5 JP 2020021796A5
- Authority
- JP
- Japan
- Prior art keywords
- wiring
- layer
- via wiring
- opening
- insulating layer
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
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Priority Applications (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2018143361A JP7068957B2 (ja) | 2018-07-31 | 2018-07-31 | 配線基板、半導体装置及び配線基板の製造方法 |
| US16/523,573 US10892217B2 (en) | 2018-07-31 | 2019-07-26 | Wiring substrate and semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2018143361A JP7068957B2 (ja) | 2018-07-31 | 2018-07-31 | 配線基板、半導体装置及び配線基板の製造方法 |
Publications (3)
| Publication Number | Publication Date |
|---|---|
| JP2020021796A JP2020021796A (ja) | 2020-02-06 |
| JP2020021796A5 true JP2020021796A5 (enExample) | 2021-07-29 |
| JP7068957B2 JP7068957B2 (ja) | 2022-05-17 |
Family
ID=69228999
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2018143361A Active JP7068957B2 (ja) | 2018-07-31 | 2018-07-31 | 配線基板、半導体装置及び配線基板の製造方法 |
Country Status (2)
| Country | Link |
|---|---|
| US (1) | US10892217B2 (enExample) |
| JP (1) | JP7068957B2 (enExample) |
Families Citing this family (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2021093417A (ja) * | 2019-12-09 | 2021-06-17 | イビデン株式会社 | プリント配線板、及び、プリント配線板の製造方法 |
| US10741483B1 (en) * | 2020-01-28 | 2020-08-11 | Advanced Semiconductor Engineering, Inc. | Substrate structure and method for manufacturing the same |
| CN112002752B (zh) | 2020-07-27 | 2023-04-21 | 北海惠科光电技术有限公司 | 源漏电极的制备方法、阵列基板的制备方法和显示机构 |
| JP7638812B2 (ja) * | 2021-07-19 | 2025-03-04 | 新光電気工業株式会社 | 配線基板及び配線基板の製造方法 |
| KR20230030995A (ko) * | 2021-08-26 | 2023-03-07 | 엘지이노텍 주식회사 | 회로 기판 및 이를 포함하는 패키지 기판 |
| KR20240059139A (ko) * | 2022-10-27 | 2024-05-07 | 삼성전기주식회사 | 인쇄회로기판 |
Family Cites Families (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP4219266B2 (ja) * | 2003-12-24 | 2009-02-04 | 日本特殊陶業株式会社 | 配線基板の製造方法 |
| US7312529B2 (en) * | 2005-07-05 | 2007-12-25 | International Business Machines Corporation | Structure and method for producing multiple size interconnections |
| JP4842864B2 (ja) * | 2007-03-15 | 2011-12-21 | 新光電気工業株式会社 | 電子装置及びその製造方法 |
| US8614143B2 (en) * | 2008-12-03 | 2013-12-24 | Texas Instruments Incorporated | Simultaneous via and trench patterning using different etch rates |
| KR101278426B1 (ko) | 2010-09-02 | 2013-06-24 | 삼성전기주식회사 | 반도체 패키지 기판의 제조방법 |
| US9245834B2 (en) * | 2012-03-16 | 2016-01-26 | Stats Chippac, Ltd. | Semiconductor device and method of forming compliant conductive interconnect structure in flipchip package |
| JP6075825B2 (ja) * | 2012-04-26 | 2017-02-08 | 新光電気工業株式会社 | パッド形成方法 |
| JP2016051747A (ja) * | 2014-08-29 | 2016-04-11 | 京セラサーキットソリューションズ株式会社 | 配線基板 |
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2018
- 2018-07-31 JP JP2018143361A patent/JP7068957B2/ja active Active
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2019
- 2019-07-26 US US16/523,573 patent/US10892217B2/en active Active