JP6938596B2 - ショットキー接触部を有する半導体デバイスを製造するための方法 - Google Patents
ショットキー接触部を有する半導体デバイスを製造するための方法 Download PDFInfo
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- JP6938596B2 JP6938596B2 JP2019203455A JP2019203455A JP6938596B2 JP 6938596 B2 JP6938596 B2 JP 6938596B2 JP 2019203455 A JP2019203455 A JP 2019203455A JP 2019203455 A JP2019203455 A JP 2019203455A JP 6938596 B2 JP6938596 B2 JP 6938596B2
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- schottky
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Description
110、210、310 半導体基板
111、211、311 基板表面/第1の面
112、212、312 第2の面
113、213 アモルファス半導体表面層
321 pアノード領域
223、323 ドリフト領域
151、251、351 ショットキー接合形成材料
152、252 第2のメタライゼーション
153、253、353 第1のメタライゼーション
354 接触メタライゼーション
160 半導体ウェーハ
161 第1の方向(黒)
162 第2の方向(赤)
163 第3の方向(緑)
371 打込み用マスク
372 エッチ・マスク
280、380 プラズマ
391 アクティブ区域
392 周辺区域/エッジ終端区域
Claims (14)
- ショットキーダイオードを製造する方法であって、
基板表面(211)を有するnドープ単結晶半導体基板(210)を設けることと、
前記基板表面(211)を粗清浄化することであって、前記粗清浄化は湿式化学粗清浄化、スパッタリング粗清浄化、反応性スパッタリング粗清浄化、またはそれらの任意の組合せ、のうちの少なくとも1つを含む、粗清浄化することと、
前記基板表面(211)を0.0133Pa(0.1mTorr)と0.11Pa(0.8mTorr)の範囲内の圧力下で容量結合プラズマに120秒未満にわたってさらすことによって前記半導体基板(210)を前処理することであって、前記容量結合プラズマに容量結合している電力が5Wから60Wの間の範囲であり、アモルファスnドープ半導体表面層(213)が形成される、前処理することと、
ショットキー接合形成材料(251)と前記半導体基板(210)との間にショットキー接触部を形成するために前記ショットキー接合形成材料(251)を前記前処理済みの基板表面(211)上にスパッタリングすることと
を含み、
前記湿式化学粗清浄化が、蒸溜水、H2O2および水酸化アンモニウムを含む第1の洗浄溶液、ならびに/または蒸溜水、H2O2および塩酸を含む第2の洗浄溶液で前記基板表面(211)を清浄化することを含み、
前記nドープ単結晶半導体基板(210)を設けること、前記基板表面(211)を粗清浄化すること、前記半導体基板(210)を前処理すること、前記ショットキー接合形成材料(251)を前記前処理済みの基板表面(211)上にスパッタリングすること、の順序で実行される、方法。 - 前記ショットキー接合形成材料(251)が、モリブデン、窒化モリブデン、チタニウム、窒化チタン、タンタル、窒化タンタル、タングステン、窒化タングステン、ドーピング濃度が少なくとも1017/cm3の多結晶シリコン、およびそれらの任意の組合せからなる群から選択される、請求項1に記載の方法。
- 前記基板表面(211)を容量結合プラズマにさらすことによる前記半導体基板(210)の前記前処理が、90秒未満にわたって実行される、請求項1または2に記載の方法。
- 前記スパッタリング粗清浄化および/または前記反応性スパッタリング粗清浄化が、前記前処理用の電力よりも大きい電力で容量結合プラズマに前記基板表面(211)をさらすことを含み、前記スパッタリング粗清浄化および/または前記反応性スパッタリング粗清浄化用の前記電力が、少なくとも40W、好ましくは少なくとも60W、より好ましくは少なくとも80Wである、請求項1から3のうちのいずれか一項に記載の方法。
- 前記基板表面(211)の前記前処理が実行され、その結果、前記基板表面(211)でのフェルミ準位が所定の値に固定される、請求項1から4のうちのいずれか一項に記載の方法。
- 前記基板表面(211)を前処理するプロセス、および前記前処理された基板表面(211)上に前記ショットキー接合形成材料(251)をスパッタリングするプロセスが、同じプロセス・チャンバ内で実行される、請求項1から5のうちのいずれか一項に記載の方法。
- 前記基板表面(211)を粗清浄化する前記プロセス、前記前処理された基板表面(211)上に前記ショットキー接合形成材料(251)をスパッタリングするプロセス、および前記スパッタリングされたショットキー接合形成材料(251)上にメタライゼーション(253)を形成するプロセスのうち、少なくとも1つのプロセスも前記同じプロセス・チャンバ内で実行される、請求項6に記載の方法。
- 前記前処理された基板表面(211)上に前記ショットキー接合形成材料(251)をスパッタリングすることが、窒素含有雰囲気中で実行される、請求項1から7のうちのいずれか一項に記載の方法。
- 前記半導体基板(210)が、SiC、Si、SiGe、GaAs、GaN、AlGaAs、GaInP、GaAsPなどのIII−V族化合物半導体、(III、III)V族化合物半導体、III(V、V)族化合物半導体、またはダイヤモンドを含む、請求項1から8のうちのいずれか一項に記載の方法。
- 前記容量結合プラズマがアルゴン・プラズマ放電である、請求項1から9のうちのいずれか一項に記載の方法。
- 基板表面(311)を有するnドープ半導体基板(310)と、
nドープ領域と接触し、かつ前記基板表面(311)内に前記nドープ領域との複数のショットキー接触部を形成するショットキー接合形成材料であって、前記ショットキー接触部のそれぞれがショットキー障壁高さを有するショットキー接合形成材料(351)と、
を含み、
前記ショットキー接触部の前記ショットキー障壁高さの標準偏差が、前記ショットキー接触部の複数の前記ショットキー障壁高さの算術平均ショットキー障壁高さの2%未満であり、
前記半導体基板(310)が、nドープ領域(323)およびpドープ領域(321)を含み、それぞれの領域は前記基板表面(311)において露出された露出部分を有し、接触メタライゼーション(354)が前記pドープ領域(321)の露出部分の上に配置される、半導体ウェーハ。 - 前記半導体基板(310)のアクティブ区域(391)内にメタライゼーション(353)をさらに含み、前記ショットキー接合形成材料(351)と前記メタライゼーション(353)は前記アクティブ区域(391)とともにアノード・メタライゼーションを有し、前記アノード・メタライゼーションは前記接触メタライゼーション(354)とオーム接触している、請求項11に記載の半導体ウェーハ。
- 前記半導体基板(310)が、SiC、Si、SiGe、GaAs、GaN、AlGaAs、GaInP、GaAsPなどのIII−V族化合物半導体、(III、III)V族化合物半導体、III(V、V)族化合物半導体、またはダイヤモンドを含む、請求項11または12に記載の半導体ウェーハ。
- 前記ショットキー接合形成材料(351)が、モリブデン、窒化モリブデン、チタニウム、窒化チタン、タンタル、窒化タンタル、タングステン、窒化タングステン、ドーピング濃度が少なくとも1017/cm3の多結晶シリコン、およびそれらの任意の組合せからなる群から選択されるスパッタリングされた金属またはスパッタリングされた金属窒化物である、請求項11から13のうちのいずれか一項に記載の半導体ウェーハ。
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